search for: ioapic_pin

...erved[0] = 0; processor.mpc_reserved[1] = 0; - return MP_processor_info_x(&processor, id); + return MP_processor_info_x(&processor, id, hotplug); } void mp_unregister_lapic(uint32_t apic_id, uint32_t cpu) @@ -888,17 +748,16 @@ void mp_unregister_lapic(uint32_t apic_i #define MP_MAX_IOAPIC_PIN 127 static struct mp_ioapic_routing { - int apic_id; - int gsi_base; - int gsi_end; - u32 pin_programmed[4]; + int gsi_base; + int gsi_end; + unsigned long pin_programmed[BITS_TO_LONGS(MP_MAX_IOAPIC_PIN + 1)]; } mp_ioapic_routing[MAX_IO_APICS]; static int mp_find_ioapic ( int...

1: IOMMU: properly check whether interrupt remapping is enabled 2: AMD IOMMU: only disable when certain IVRS consistency checks fail 3: VT-d: deal with 5500/5520/X58 errata Patch 1 and 2 are version 2 of a previously submitted, then withdrawn patch following up after XSA-36. Patch 3 is version 3 of a patch previously sent by Malcolm and Andrew. Signed-off-by: Jan Beulich

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine