search for: ioapic_lock

...n eu; + eu.w1 = (*read)(apic, 0x10 + 2 * pin); + eu.w2 = (*read)(apic, 0x11 + 2 * pin); + return eu.entry; +} + +static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin, int raw) +{ + struct IO_APIC_route_entry entry; + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) +...

...n eu; + eu.w1 = (*read)(apic, 0x10 + 2 * pin); + eu.w2 = (*read)(apic, 0x11 + 2 * pin); + return eu.entry; +} + +static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin, int raw) +{ + struct IO_APIC_route_entry entry; + unsigned long flags; + + spin_lock_irqsave(&ioapic_lock, flags); + entry = __ioapic_read_entry(apic, pin, raw); + spin_unlock_irqrestore(&ioapic_lock, flags); + return entry; +} + +static void +__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e) +{ + void (*write)(unsigned int, unsigned int, unsigned int) +...

..._APIC_irq(irq, 0x00010000, 0x00008000); -} - -/* mask = 0, trigger = 1 */ -static void __unmask_and_level_IO_APIC_irq (unsigned int irq) -{ - __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); -} - -static void mask_IO_APIC_irq (unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioapic_lock, flags); - __mask_IO_APIC_irq(irq); - spin_unlock_irqrestore(&ioapic_lock, flags); -} - -static void unmask_IO_APIC_irq (unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioapic_lock, flags); - __unmask_IO_APIC_irq(irq); - spin_unlock_irqrestore(&ioapic_lock, flags); -}...

..._APIC_irq(irq, 0x00010000, 0x00008000); -} - -/* mask = 0, trigger = 1 */ -static void __unmask_and_level_IO_APIC_irq (unsigned int irq) -{ - __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); -} - -static void mask_IO_APIC_irq (unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioapic_lock, flags); - __mask_IO_APIC_irq(irq); - spin_unlock_irqrestore(&ioapic_lock, flags); -} - -static void unmask_IO_APIC_irq (unsigned int irq) -{ - unsigned long flags; - - spin_lock_irqsave(&ioapic_lock, flags); - __unmask_IO_APIC_irq(irq); - spin_unlock_irqrestore(&ioapic_lock, flags); -}...

...APIC_route_entry *entry; + unsigned long flags; + int apic,i; + + ioapic_pm_state_alloc(); + + if (ioapic_pm_state == NULL){ + printk("can not suspend ioapic due to lack of memory\n"); + return 1; + } + + entry = ioapic_pm_state; + spin_lock_irqsave(&ioapic_lock, flags); + for (apic = 0; apic < nr_ioapics; apic++) { + for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) { + *(((int *)entry) + 1) = io_apic_read(apic, 0x11 + 2 * i); + *(((int *)entry) + 0) = io_apic_read(apic, 0x10 + 2 * i); + } + } +...

The formatting of the IO-APIC debug key info has niggled me for a while, and with the latest interrupt bug I am chasing, has finally motivated me to fix it. The attached patch causes all columns to line up, and removes the comma which served no purpose in combination with the spaces already present. -- Andrew Cooper - Dom0 Kernel Engineer, Citrix XenServer T: +44 (0)1223 225 900,

Patch 1 removes CONFIG_SMP Patch 2 removes separate smp_{,r,w}mb()s as a result of patch 1 Patch 4 removes __ia64__ defines from the x86 arch tree Patch 3 is related to patch 4 and changes the VIOAPIC to emulate version 0x20 as a performance gain. It preceeds Patch 4 so as to be more clear about the functional change. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Hi Ingo, Here''s the chunk of patches to add Xen Dom0 support (it''s probably worth creating a new xen/dom0 topic branch for it). A dom0 Xen domain is basically the same as a normal domU domain, but it has extra privileges to directly access hardware. There are two issues to deal with: - translating to and from the domain''s pseudo-physical addresses and real machine