Displaying 14 results from an estimated 14 matches for "io_base".
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iov_base
2012 Sep 11
2
[PATCH RFC 5/8] ns16550: MMIO adjustments
...gt;
#include <asm/io.h>
+#ifdef CONFIG_X86
+#include <asm/fixmap.h>
+#endif
/*
* Configure serial port with a string:
@@ -37,7 +40,7 @@ string_param("com2", opt_com2);
static struct ns16550 {
int baud, clock_hz, data_bits, parity, stop_bits, irq;
unsigned long io_base; /* I/O port or memory-mapped I/O address. */
- char *remapped_io_base; /* Remapped virtual address of mmap I/O. */
+ char __iomem *remapped_io_base; /* Remapped virtual address of MMIO. */
/* UART with IRQ line: interrupt-driven I/O. */
struct irqaction irqaction;
/* UAR...
2013 Sep 13
10
[PATCH RFC 0/8] xen/arm: initial cubieboard2 support.
See http://www.gossamer-threads.com/lists/xen/devel/297170 for some
information on how to get this going.
I''ve rebased and addressed the review comments.
As before several of the patches are not to be applied because they can
be done better using infrastructure from Julien''s "Allow Xen to boot
with a raw Device Tree" patch. They are included for completeness.
With
2005 Oct 02
3
[Sorta OT] Eicon DIVA with asterisk@home
...has reported the error :
DIVA Server Driver - initialising
DIVA Server Driver - Version 2.0.16
Divas: DIVA Server BRI (U) Found
Divas: DIVA I/O Base already in use 0xf1000000-0xf100001f
Divas: 0 cards detected
Divas: Not loaded
(here's the code that produces it ...)
if (check_region(Card.io_base, 0x20))
{
printk(KERN_WARNING "Divas: DIVA I/O Base already in use
0x%x-0x%x\n", Card.io_base, Card.io_base + 0x1F);
wDeviceIndex++;
continue;
}
cat /proc/iomem shows :
f0200000-f020ffff : PCI device 1133:e013 (Eicon Technology Corporation)
f0210000-...
2013 Sep 20
20
[PATCH v3 0/7] support for cubieboard2 / sunxi processors
See http://www.gossamer-threads.com/lists/xen/devel/297170 for some
information on how to get this going.
I''ve rebased and addressed the review comments.
With this rebase I''ve picked up some patches from Julien which were
required to do things properly, so the gic v7 and device blacklisting
patches have been changed to use the proper mechanisms.
Previously I was able to boot
2012 Sep 11
2
[PATCH 6/8] ns16550: PCI initialization adjustments
...}
bar = pci_conf_read32(0, b, d, f,
PCI_BASE_ADDRESS_0 + bar_idx*4);
@@ -504,7 +509,9 @@ pci_uart_config (struct ns16550 *uart, i
uart->bar = bar;
uart->bar_idx = bar_idx;
uart->io_base = bar & ~PCI_BASE_ADDRESS_SPACE_IO;
- uart->irq = 0;
+ uart->irq = pci_conf_read8(0, b, d, f, PCI_INTERRUPT_PIN) ?
+ pci_conf_read8(0, b, d, f, PCI_INTERRUPT_LINE) : 0;
+printk("COM%d: BAR=%04x IRQ=%d\n", bar_idx + 1, bar, uart-&g...
2018 Jul 27
1
[PATCH] drm: qxl: Fix error handling at qxl_device_init
...it(&qdev->ddev, drv, &pdev->dev);
- if (r)
- return r;
+ if (r) {
+ pr_err("Unable to init drm dev");
+ goto error;
+ }
qdev->ddev.pdev = pdev;
pci_set_drvdata(pdev, &qdev->ddev);
@@ -121,6 +123,11 @@ int qxl_device_init(struct qxl_device *qdev,
qdev->io_base = pci_resource_start(pdev, 3);
qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
+ if (!qdev->vram_mapping) {
+ pr_err("Unable to create vram_mapping");
+ r = -ENOMEM;
+ goto error;
+ }
if (pci_resource_len(pdev, 4) > 0) {
/*...
2018 Feb 16
0
[PATCH 1/4] qxl: remove qxl_io_log()
...st char *fmt, ...)
-{
- va_list args;
-
- va_start(args, fmt);
- vsnprintf(qdev->ram_header->log_buf, QXL_LOG_BUF_SIZE, fmt, args);
- va_end(args);
- /*
- * DO not do a DRM output here - this will call printk, which will
- * call back into qxl for rendering (qxl_fb)
- */
- outb(0, qdev->io_base + QXL_IO_LOG);
-}
-
void qxl_io_reset(struct qxl_device *qdev)
{
outb(0, qdev->io_base + QXL_IO_RESET);
@@ -428,19 +411,6 @@ void qxl_io_reset(struct qxl_device *qdev)
void qxl_io_monitors_config(struct qxl_device *qdev)
{
- qxl_io_log(qdev, "%s: %d [%dx%d+%d+%d]\n", __func__,...
2018 Apr 20
0
[PATCH v2 1/4] qxl: remove qxl_io_log()
...st char *fmt, ...)
-{
- va_list args;
-
- va_start(args, fmt);
- vsnprintf(qdev->ram_header->log_buf, QXL_LOG_BUF_SIZE, fmt, args);
- va_end(args);
- /*
- * DO not do a DRM output here - this will call printk, which will
- * call back into qxl for rendering (qxl_fb)
- */
- outb(0, qdev->io_base + QXL_IO_LOG);
-}
-
void qxl_io_reset(struct qxl_device *qdev)
{
outb(0, qdev->io_base + QXL_IO_RESET);
@@ -428,19 +411,6 @@ void qxl_io_reset(struct qxl_device *qdev)
void qxl_io_monitors_config(struct qxl_device *qdev)
{
- qxl_io_log(qdev, "%s: %d [%dx%d+%d+%d]\n", __func__,...
2008 Jan 18
7
[Patch] Make memory hole for PCI Express bigger and prevent roll-over
...0
+++ b/tools/firmware/hvmloader/hvmloader.c Fri Jan 18 15:47:01 2008 -0500
@@ -183,7 +183,7 @@ static void apic_setup(void)
static void pci_setup(void)
{
- uint32_t devfn, bar_reg, bar_data, bar_sz, cmd;
+ uint32_t devfn, bar_reg, bar_data, bar_sz, cmd, mem_base_test;
uint32_t *base, io_base = 0xc000, mem_base = HVM_BELOW_4G_MMIO_START;
uint16_t class, vendor_id, device_id;
unsigned int bar, pin, link, isa_irq;
@@ -254,16 +254,34 @@ static void pci_setup(void)
base = &mem_base;
bar_sz &= PCI_BASE_ADDRESS_MEM_MASK;...
2010 Jun 14
0
NV30 (FX 5200 Ultra) OUT_RINGp and initial four GEM objects are mapped to the GART instead of System RAM - is that proper?
...ch ends up calling
'NVAccelInitContextSurfaces' function that tries to write to the
second of the above mentioned objects. That triggers the ttm_bo_vm_fault
which:
a). Determines that since the offset is within the TT pool, and that pool
is a PCI device it sets the io_base to ec00000 and with an offset of
0x24000 (don't know yet why that offset value). Then it attaches to the
VMA the PFN for the 0xec024 and returns it to the userspace.
b). The NVAccelInitContNVAccelInitContextSurfaceextSurface writes to the
GART values that look like they be...
2012 Oct 08
21
[PATCH 00/14] Remove old_portio users for memory region PIO mapping
When running on PowerPC, we don''t have native PIO support. There are a few hacks
around to enable PIO access on PowerPC nevertheless.
The most typical one is the isa-mmio device. It takes MMIO requests and converts
them to PIO requests on the (QEMU internal) PIO bus.
This however is not how real hardware works and it limits us in the ability to
spawn eventfd''s on PIO ports
2011 Jun 02
0
[PATCH] pci: Use pr_<level> and pr_fmt
...urn 1;
}
}
@@ -1251,7 +1261,8 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st
u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
- dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
+ dev_func, io_base, io_length, mem_base, mem_length,
+ pre_mem_base, pre_mem_length,
primary_bus, secondary_bus, max_bus);
/* If this entry isn't for our controller's bus, ignore it */
@@ -1270,7 +1281,8...
2011 Jun 02
0
[PATCH] pci: Use pr_<level> and pr_fmt
...urn 1;
}
}
@@ -1251,7 +1261,8 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st
u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
- dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
+ dev_func, io_base, io_length, mem_base, mem_length,
+ pre_mem_base, pre_mem_length,
primary_bus, secondary_bus, max_bus);
/* If this entry isn't for our controller's bus, ignore it */
@@ -1270,7 +1281,8...
2011 Jun 02
0
[PATCH] pci: Use pr_<level> and pr_fmt
...urn 1;
}
}
@@ -1251,7 +1261,8 @@ int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_st
u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
- dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
+ dev_func, io_base, io_length, mem_base, mem_length,
+ pre_mem_base, pre_mem_length,
primary_bus, secondary_bus, max_bus);
/* If this entry isn't for our controller's bus, ignore it */
@@ -1270,7 +1281,8...