Displaying 8 results from an estimated 8 matches for "io_apic_writ".
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io_apic_write
2011 May 09
1
Bug#625438: [PATCH] xen: ioapic: avoid gcc 4.6 warnings about uninitialised variables
...entry = __ioapic_read_entry(apic, pin, raw);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
+ return entry;
+}
+
+static void
+__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
+{
+ void (*write)(unsigned int, unsigned int, unsigned int)
+ = raw ? __io_apic_write : io_apic_write;
+ union entry_union eu = {{0, 0}};
+
+ eu.entry = e;
+ (*write)(apic, 0x11 + 2*pin, eu.w2);
+ (*write)(apic, 0x10 + 2*pin, eu.w1);
+}
+
+static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
+{
+ unsigned long flags;
+ spin_lock...
2011 May 09
1
Bug#625438: [PATCH] xen: ioapic: avoid gcc 4.6 warnings about uninitialised variables
...entry = __ioapic_read_entry(apic, pin, raw);
+ spin_unlock_irqrestore(&ioapic_lock, flags);
+ return entry;
+}
+
+static void
+__ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
+{
+ void (*write)(unsigned int, unsigned int, unsigned int)
+ = raw ? __io_apic_write : io_apic_write;
+ union entry_union eu = {{0, 0}};
+
+ eu.entry = e;
+ (*write)(apic, 0x11 + 2*pin, eu.w2);
+ (*write)(apic, 0x10 + 2*pin, eu.w1);
+}
+
+static void ioapic_write_entry(int apic, int pin, int raw, struct IO_APIC_route_entry e)
+{
+ unsigned long flags;
+ spin_lock...
2007 Apr 18
2
refactoring io_apic.c
...c_read(apic, 0x11 + 2 * pin);
- spin_unlock_irqrestore(&ioapic_lock, flags);
- if (entry.delivery_mode == dest_SMI)
- return;
-
- /*
- * Disable it in the IO-APIC irq-routing table:
- */
- memset(&entry, 0, sizeof(entry));
- entry.mask = 1;
- spin_lock_irqsave(&ioapic_lock, flags);
- io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
- io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
- spin_unlock_irqrestore(&ioapic_lock, flags);
-}
-
-static void clear_IO_APIC (void)
-{
- int apic, pin;
-
- for (apic = 0; apic < nr_ioapics; apic++)
- for (pin = 0; pin...
2007 Apr 18
2
refactoring io_apic.c
...c_read(apic, 0x11 + 2 * pin);
- spin_unlock_irqrestore(&ioapic_lock, flags);
- if (entry.delivery_mode == dest_SMI)
- return;
-
- /*
- * Disable it in the IO-APIC irq-routing table:
- */
- memset(&entry, 0, sizeof(entry));
- entry.mask = 1;
- spin_lock_irqsave(&ioapic_lock, flags);
- io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
- io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
- spin_unlock_irqrestore(&ioapic_lock, flags);
-}
-
-static void clear_IO_APIC (void)
-{
- int apic, pin;
-
- for (apic = 0; apic < nr_ioapics; apic++)
- for (pin = 0; pin...
2012 Oct 18
3
[PATCH 1/1] keep iommu disabled until iommu_setup is called
...tch "x86-64: detect processors subject to AMD erratum #121 and refuse to
boot." since xen 4.1.3 and results in the following stacktrace:
find_iommu_for_device
amd_iommu_ioapic_update_ire
timer_interrupt
enable_8259_A_irq
do_IRQ
printk_start_of_line
acpi_os_printf
io_apic_write
__ioapic_write_entry
ioapic_write_entry
__clear_IO_APIC_pin
clear_IO_APIC
disable_IO_APIC
__stop_this_cpu
smp_send_stop
machine_restart
panic
tasklet_schedule_on_cpu
display_cacheinfo
init_amd
generic_identify
identify_cpu
_start_xen
_high_start
Th...
2007 May 15
3
[PATCH 1/12] Add suspend/resume to devices owned by Xen
...= ioapic_pm_state;
+
+ spin_lock_irqsave(&ioapic_lock, flags);
+ for (apic = 0; apic < nr_ioapics; apic++){
+ reg_00.raw = io_apic_read(apic, 0);
+ if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) {
+ reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
+ io_apic_write(apic, 0, reg_00.raw);
+ }
+ for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
+ io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
+ io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
+ }
+ }
+ spin_unlock_irqrestore(&ioapic_loc...
2012 Oct 18
0
[PATCH 0/1] fix xen-crash at panic()-call during boot
...1 and refuse to boot."
Instead of the actual panic-message from the patch the following stacktrace
appears (i typed it down from screen, so it might contain typos)
find_iommu_for_device
amd_iommu_ioapic_update_ire
timer_interrupt
enable_8259_A_irq
do_IRQ
printk_start_of_line
acpi_os_printf
io_apic_write
__ioapic_write_entry
ioapic_write_entry
__clear_IO_APIC_pin
clear_IO_APIC
disable_IO_APIC
__stop_this_cpu
smp_send_stop
machine_restart
panic
tasklet_schedule_on_cpu
display_cacheinfo
init_amd
generic_identify
identify_cpu
_start_xen
_high_start
Panic on CPU 0:
Xen BUG at pci_amd_iommu.c:33
====...
2008 Nov 13
69
[PATCH 00 of 38] xen: add more Xen dom0 support
Hi Ingo,
Here''s the chunk of patches to add Xen Dom0 support (it''s probably
worth creating a new xen/dom0 topic branch for it).
A dom0 Xen domain is basically the same as a normal domU domain, but
it has extra privileges to directly access hardware. There are two
issues to deal with:
- translating to and from the domain''s pseudo-physical addresses and
real machine