Displaying 3 results from an estimated 3 matches for "invalidateliveness".
2015 Feb 04
2
[LLVMdev] Handling of KILL instructions.
...KILL %V0, %V0_64<imp-use,kill>
PseudoReturn64 %RA_64
In this case we would like to move the AND64 instruction after the KILL
instruction (generated from an identity COPY).
What is the right thing to do with the KILL instruction given the fact that
the machine function pass calls TRI.invalidateLiveness()? Can we simply
delete any KILL instruction we want? Or, can we ignore them as long as we
don't request any register liveness analysis in subsequent machine function
passes?
-- Vasileios Kalintiris
2017 Feb 16
2
Print Register Liveness Information
Note that this only works for targets that say TargetRegisterInfo::trackLivenessAfterRegAlloc()== true.
> On Feb 16, 2017, at 1:21 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Hi Anitha,
>
> The liveness information is usually dropped after regalloc.
> Therefore the short answer is no, this information is not available before producing
2012 Oct 29
1
[LLVMdev] Data flow/liveness in register pairs
Hello,
Consider this code (this is all after register allocation):
R0<def> = ... R0 // Set lower half (based on the previous value)
R1<def> = ... // Set upper half
... = R0_R1 // Use the pair
It is my understanding that the use of the whole pair will need to have
some sort of a reaching def, i.e. the code will need at least those flags:
R0<def> =