Displaying 7 results from an estimated 7 matches for "intsimpl".
Did you mean:
intsimple
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...perands are translated into
the encoding fields. Can someone please explain the following snippet from
the PPC back-end.
The AND instruction in PPC is defined as:
1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
1012 "and $rA, $rS, $rB", IntSimple,
1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
Okay, so rA, rS, and rB are register operands.
The TableGen classes are defined as:
315 class XForm_base_r3xo_swapped
316 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
317 In...
2012 Jul 24
2
[LLVMdev] Instruction Encodings in TableGen
...explain the following snippet
> from
> > the PPC back-end.
> >
> > The AND instruction in PPC is defined as:
> >
> > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS,
> GPRC:$rB),
> > 1012 "and $rA, $rS, $rB", IntSimple,
> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
> >
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6&g...
2012 Jul 24
0
[LLVMdev] Instruction Encodings in TableGen
...e encoding fields. Can someone please explain the following snippet from
> the PPC back-end.
>
> The AND instruction in PPC is defined as:
>
> 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
> 1012 "and $rA, $rS, $rB", IntSimple,
> 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
>
> Okay, so rA, rS, and rB are register operands.
>
> The TableGen classes are defined as:
>
> 315 class XForm_base_r3xo_swapped
> 316 <bits<6> opcode, bits<10> xo, dag OOL...
2012 Jul 25
2
[LLVMdev] Instruction Encodings in TableGen
...gt;> from
>> > the PPC back-end.
>> >
>> > The AND instruction in PPC is defined as:
>> >
>> > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS,
>> GPRC:$rB),
>> > 1012 "and $rA, $rS, $rB", IntSimple,
>> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
>> >
>> > Okay, so rA, rS, and rB are register operands.
>> >
>> > The TableGen classes are defined as:
>> >
>> > 315 class XForm_base_r3xo_swapped
>>...
2012 Jul 25
0
[LLVMdev] Instruction Encodings in TableGen
...one please explain the following snippet from
> > the PPC back-end.
> >
> > The AND instruction in PPC is defined as:
> >
> > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
> > 1012 "and $rA, $rS, $rB", IntSimple,
> > 1013 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
> >
> > Okay, so rA, rS, and rB are register operands.
> >
> > The TableGen classes are defined as:
> >
> > 315 class XForm_base_r3xo_swapped
> > 316 <bits<6&g...
2012 Jul 27
0
[LLVMdev] Instruction Encodings in TableGen
...PPC back-end.
> >> >
> >> > The AND instruction in PPC is defined as:
> >> >
> >> > 1011 def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS,
> >> GPRC:$rB),
> >> > 1012 "and $rA, $rS, $rB", IntSimple,
> >> > 1013 [(set GPRC:$rA, (and GPRC:$rS,
> >> > GPRC:$rB))]>;
> >> >
> >> > Okay, so rA, rS, and rB are register operands.
> >> >
> >> > The TableGen classes are defined as:
> >> >
> >...
2013 Jul 09
1
[LLVMdev] Optimization issue for target's offset field of load operation in DAGSelection
I am working on an experimental target and trying to make sure that
the load offset field is used to the best way. There appears to be
some control over the architecture's offset range and whether the
offset is too large and needs to be lowered/converted into a separate
sequence of operations in DAGSelection?
Can someone point me to what might be the case?
For example, the difference between