Displaying 9 results from an estimated 9 matches for "intr_mask".
2014 Sep 08
1
[PATCH] gpio: rename g92 class to g94
...2 stat0 = nv_rd32(gpio, 0x00e050) & intr0;
- u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1;
- *lo = (stat1 & 0xffff0000) | (stat0 >> 16);
- *hi = (stat1 << 16) | (stat0 & 0x0000ffff);
- nv_wr32(gpio, 0x00e054, intr0);
- nv_wr32(gpio, 0x00e074, intr1);
-}
-
-void
-nv92_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data)
-{
- u32 inte0 = nv_rd32(gpio, 0x00e050);
- u32 inte1 = nv_rd32(gpio, 0x00e070);
- if (type & NVKM_GPIO_LO)
- inte0 = (inte0 & ~(mask << 16)) | (data << 16);
- if (type & NVKM_GPIO_HI)
- inte0 = (inte0 & ~(mask &...
2009 Oct 27
1
[PATCH 2/4] megasas: LSI MegaRAID SAS HBA emulation
...* Register definitions */
+#define MEGASAS_INBOUND_MSG_0 0x0010
+#define MEGASAS_INBOUND_MSG_1 0x0014
+#define MEGASAS_OUTBOUND_MSG_0 0x0018
+#define MEGASAS_OUTBOUND_MSG_1 0x001C
+#define MEGASAS_INBOUND_DOORBELL 0x0020
+#define MEGASAS_INBOUND_INTR_STATUS 0x0024
+#define MEGASAS_INBOUND_INTR_MASK 0x0028
+#define MEGASAS_OUTBOUND_DOORBELL 0x002C
+#define MEGASAS_OUTBOUND_INTR_STATUS 0x0030
+#define MEGASAS_OUTBOUND_INTR_MASK 0x0034
+#define MEGASAS_INBOUND_QUEUE_PORT 0x0040
+#define MEGASAS_OUTBOUND_QUEUE_PORT 0x0044
+#define MEGASAS_OUTBOUND_DOORBELL_CLEAR 0x00A0
+#define MEGASAS_OUT...
2009 Oct 27
1
[PATCH 2/4] megasas: LSI MegaRAID SAS HBA emulation
...* Register definitions */
+#define MEGASAS_INBOUND_MSG_0 0x0010
+#define MEGASAS_INBOUND_MSG_1 0x0014
+#define MEGASAS_OUTBOUND_MSG_0 0x0018
+#define MEGASAS_OUTBOUND_MSG_1 0x001C
+#define MEGASAS_INBOUND_DOORBELL 0x0020
+#define MEGASAS_INBOUND_INTR_STATUS 0x0024
+#define MEGASAS_INBOUND_INTR_MASK 0x0028
+#define MEGASAS_OUTBOUND_DOORBELL 0x002C
+#define MEGASAS_OUTBOUND_INTR_STATUS 0x0030
+#define MEGASAS_OUTBOUND_INTR_MASK 0x0034
+#define MEGASAS_INBOUND_QUEUE_PORT 0x0040
+#define MEGASAS_OUTBOUND_QUEUE_PORT 0x0044
+#define MEGASAS_OUTBOUND_DOORBELL_CLEAR 0x00A0
+#define MEGASAS_OUT...
2017 Apr 02
1
[PATCH] drm/nouveau: enable interrupts on cards with 32 intr lines
...au/nvkm/subdev/gpio/base.c
@@ -164,7 +164,7 @@ static int
nvkm_gpio_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_gpio *gpio = nvkm_gpio(subdev);
- u32 mask = (1 << gpio->func->lines) - 1;
+ u32 mask = (1ULL << gpio->func->lines) - 1;
gpio->func->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0);
gpio->func->intr_stat(gpio, &mask, &mask);
--
2.11.0
2020 Oct 30
6
[PATCH 0/5] Improve Robust Channel (RC) recovery for Turing
This is an initial series of patches to improve channel recovery on Turing GPUs
with the goal of improving reliability enough to eventually enable SVM for
Turing. It's likely follow up patches will be required to fully address problems
with less trivial workloads than what I have been able to test thus far.
This series primarily addresses a number of hardware changes to interrupt layout
and
2017 Mar 29
0
[PATCH 10/15] mc: add GP10B support
..._unlock_irqrestore(&mc->lock, flags);
}
-static void
+void
gp100_mc_intr_rearm(struct nvkm_mc *base)
{
struct gp100_mc *mc = gp100_mc(base);
@@ -64,7 +64,7 @@ gp100_mc_intr_rearm(struct nvkm_mc *base)
spin_unlock_irqrestore(&mc->lock, flags);
}
-static void
+void
gp100_mc_intr_mask(struct nvkm_mc *base, u32 mask, u32 intr)
{
struct gp100_mc *mc = gp100_mc(base);
@@ -87,13 +87,14 @@ gp100_mc = {
};
int
-gp100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc)
+gp100_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device,
+ int index,...
2018 Mar 10
17
[RFC PATCH 00/13] SVM (share virtual memory) with HMM in nouveau
From: Jérôme Glisse <jglisse at redhat.com>
(mm is cced just to allow exposure of device driver work without ccing
a long list of peoples. I do not think there is anything usefull to
discuss from mm point of view but i might be wrong, so just for the
curious :)).
git://people.freedesktop.org/~glisse/linux branch: nouveau-hmm-v00
2006 Apr 12
1
powerd not behaving with an Asus A8V-MX and Athlon 64 X2 3800+
...irewire.sbp.exclusive_login: 1
hw.firewire.sbp.login_delay: 1000
hw.firewire.sbp.scan_delay: 500
hw.firewire.sbp.use_doorbell: 0
hw.firewire.sbp.tags: 0
hw.pccard.debug: 0
hw.pccard.cis_debug: 0
hw.cbb.start_memory: 2281701376
hw.cbb.start_16_io: 256
hw.cbb.start_32_io: 4096
hw.cbb.debug: 0
hw.pcic.intr_mask: 57016
hw.pci.enable_io_modes: 1
hw.pci.do_power_nodriver: 0
hw.pci.do_power_resume: 1
hw.pci.host_mem_start: 2147483648
hw.pci.irq_override_mask: 57080
hw.wi.txerate: 0
hw.wi.debug: 0
hw.xe.debug: 0
hw.intr_storm_threshold: 500
hw.availpages: 522022
hw.bus.devctl_disable: 0
hw.dc_quick: 1
hw.ste.r...
2017 Mar 29
15
[PATCH 00/15] Support for GP10B chipset
GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for
its base engines after reworking secboot a bit to accomodate its calling
convention better.
This patchset has been tested rendering simple off-screen buffers using Mesa
and yielded the expected result.
Alexandre Courbot (15):
secboot: allow to boot multiple falcons
secboot: pass instance to LS firmware loaders
secboot: