Displaying 9 results from an estimated 9 matches for "intr_en".
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intr_len
2013 Aug 12
2
[PATCH] drm/nouveau: fix ltcg memory initialization after suspend
...ag_base;
}
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
@@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
- nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
-
ret = nvc0_ltcg_init_tag_ram(pfb, priv);
if (ret)
return ret;
@@ -209,13 +204,36 @@ nvc0_ltcg_dtor(struct nouveau_object *object)
nouveau_ltcg_destroy(ltcg);
}
+int
+nvc0_ltcg_init(struct nouveau_object *object)
+{
+ struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)o...
2013 Jun 04
0
[PATCH] nouveau: Load firmware for BSP/VP engines on NV84-NV96, NVA0
...r32(device, 0x103d08, 0x0fffffff); /* ?? */
> +
> + nv_wr32(device, 0x103d28, 0x90044); /* ?? */
> + nv_mask(device, 0x2090, 0xf0000000, 0x8 << 28); /* PFIFO.UNK90 */
> + nv_wr32(device, 0x103c20, 0x3f); /* INTR */
> + nv_wr32(device, 0x103d84, 0x3f); /* INTR_EN */
> +
> + nv_debug(priv, "Loading firmware to address: 0x%llx\n",
> + priv->gpu_fw->addr);
> +
> + for (i = 0; i < priv->fw_size / 4; i++)
> + nv_wo32(priv->gpu_fw, i * 4, priv->fw[i]);
> +
> + nv_wr...
2013 Aug 07
1
[PATCH] drm/nouveau: fix ltcg memory corruptions
...ag_base;
}
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
@@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
- nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
-
ret = nvc0_ltcg_init_tag_ram(pfb, priv);
if (ret)
return ret;
@@ -209,13 +204,36 @@ nvc0_ltcg_dtor(struct nouveau_object *object)
nouveau_ltcg_destroy(ltcg);
}
+int
+nvc0_ltcg_init(struct nouveau_object *object)
+{
+ struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)o...
2013 Jun 03
4
[PATCH] nouveau: Load firmware for BSP/VP engines on NV84-NV96, NVA0
...32(device, 0x103d10, 0x1fffffff); /* ?? */
+ nv_wr32(device, 0x103d08, 0x0fffffff); /* ?? */
+
+ nv_wr32(device, 0x103d28, 0x90044); /* ?? */
+ nv_mask(device, 0x2090, 0xf0000000, 0x8 << 28); /* PFIFO.UNK90 */
+ nv_wr32(device, 0x103c20, 0x3f); /* INTR */
+ nv_wr32(device, 0x103d84, 0x3f); /* INTR_EN */
+
+ nv_debug(priv, "Loading firmware to address: 0x%llx\n",
+ priv->gpu_fw->addr);
+
+ for (i = 0; i < priv->fw_size / 4; i++)
+ nv_wo32(priv->gpu_fw, i * 4, priv->fw[i]);
+
+ nv_wr32(device, 0x103cc0, priv->gpu_fw->addr >> 8); /* REGION_BASE */
+ nv_wr...
2013 Aug 14
0
[PATCH] drm/nvc0-/ltcg: fix ltcg memory initialization after suspend
...ag_base;
}
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
@@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
- nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
-
ret = nvc0_ltcg_init_tag_ram(pfb, priv);
if (ret)
return ret;
@@ -209,13 +204,35 @@ nvc0_ltcg_dtor(struct nouveau_object *object)
nouveau_ltcg_destroy(ltcg);
}
+static int
+nvc0_ltcg_init(struct nouveau_object *object)
+{
+ struct nouveau_ltcg *ltcg = (struct nouveau_l...
2013 Aug 12
0
[PATCH] drm/nouveau: fix ltcg memory initialization after suspend
...iv->tags, 0, priv->num_tags, 1);
>
> @@ -182,8 +179,6 @@ nvc0_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
> }
> priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
>
> - nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
> -
> ret = nvc0_ltcg_init_tag_ram(pfb, priv);
> if (ret)
> return ret;
> @@ -209,13 +204,36 @@ nvc0_ltcg_dtor(struct nouveau_object *object)
> nouveau_ltcg_destroy(ltcg);
> }
>
> +int
> +nvc0_ltcg_init(struct no...
2013 Jun 23
0
[PATCH v2] nouveau: Load firmware for BSP/VP engines on NV84-NV96, NVA0
...0xd08, 0x0fffffff); /* ?? */
+
+ nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
+ nv_mask(xtensa, 0x2090,
+ 0xf << (xtensa->fifo_nibble * 4),
+ 0x8 << (xtensa->fifo_nibble * 4)); /* PFIFO.UNK90 */
+ nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
+ nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
+
+ nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
+ nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
+ nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
+
+ tmp = nv_rd32(xtensa, 0x0);
+ nv_wo32(xtensa, 0xde0, tmp); /* S...
2015 Nov 15
21
[Bug 92961] New: Xorg freezes (only mouse and ssh are still working)
https://bugs.freedesktop.org/show_bug.cgi?id=92961
Bug ID: 92961
Summary: Xorg freezes (only mouse and ssh are still working)
Product: xorg
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: critical
Priority: high
Component: Driver/nouveau
2013 Mar 27
3
[PATCH 1/4] drm/nvc0: implement VRAM compression
...ne,
if (ret)
return ret;
- priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 24;
+ priv->part_nr = nv_rd32(priv, 0x022438);
+ priv->part_mask = nv_rd32(priv, 0x022554);
+
+ priv->subp_nr = nv_rd32(priv, 0x17e8dc) >> 28;
+
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
+ ret = nvc0_ltcg_init_tag_ram(pfb, priv);
+ if (ret)
+ return ret;
+
+ priv->base.tags_alloc = nvc0_ltcg_tags_alloc;
+ priv->base.tags_free = nvc0_ltcg_tags_free;
+ priv->base.tags_clear = nvc0_ltcg_tags_clear;
+
nv_subdev(priv)->intr = nvc0_ltcg_intr;
return 0;...