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...uctions that implicitly define a condition register: class isDOT { list<Register> Defs = [CR0]; bit RC = 1; } and this gets used on instructions such as: def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD, $rA, $imm", IntGeneral, []>, isDOT; but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this: let Defs = [CARRY] in def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), "addic. $rD,...

...ster: > > class isDOT { > list<Register> Defs = [CR0]; > bit RC = 1; > } > > and this gets used on instructions such as: > > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), > "addic. $rD, $rA, $imm", IntGeneral, > []>, isDOT; > > but there is a small problem. If these instructions are also part of a larger block which also defines registers, like this: > > let Defs = [CARRY] in > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm), >...

...t;Register> Defs = [CR0]; > > bit RC = 1; > > } > > > > and this gets used on instructions such as: > > > > def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, > > s16imm:$imm), > > "addic. $rD, $rA, $imm", IntGeneral, > > []>, isDOT; > > > > but there is a small problem. If these instructions are also part > > of a larger block which also defines registers, like this: > > > > let Defs = [CARRY] in > > def ADDICo : DForm_2<13, (outs GPRC:$rD),...

...FRACC, >>>>>> + IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, > LWB, >>>>>> + FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], >>>>>> + [GPR_Bypass, FPR_Bypass], [ >>>>>> + InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>, >>>>>> + InstrStage<1, [PDCD1, PDCD2]>, >>>>>> + InstrStage<1, [DISS1, DISS2]>, >>>>>> + InstrStage&lt...