Displaying 6 results from an estimated 6 matches for "interp_linear".
2009 Jun 24
0
[PATCH] nv50: fix previous patches
...an DEPR output be mapped to another register ?
+ * (currently it's index is that of the last color's register + 1)
*
* 1298 = 0x00000004; or 0x00000005 if DEPR is written
*
@@ -444,7 +445,7 @@ set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e)
#define INTERP_LINEAR 0
-#define INTERP_FLAT 1
+#define INTERP_FLAT 1
#define INTERP_PERSPECTIVE 2
#define INTERP_CENTROID 4
@@ -1852,6 +1853,10 @@ prep_inspect_insn(struct nv50_pc *pc, const union tgsi_full_token *tok,
dst = &insn->FullDstRegisters[0].DstRegister;
mask = dst->WriteMask;
+#ifdef...
2015 May 26
2
[PATCH 2/2] nv30/draw: switch varying hookup logic to know about texcoords
...0_draw.c b/src/gallium/drivers/nouveau/nv30/nv30_draw.c
> index a681135..03c0c70 100644
> --- a/src/gallium/drivers/nouveau/nv30/nv30_draw.c
> +++ b/src/gallium/drivers/nouveau/nv30/nv30_draw.c
> @@ -230,22 +230,24 @@ static const struct {
> [TGSI_SEMANTIC_BCOLOR ] = { EMIT_4F, INTERP_LINEAR , 1, 3, 0x00000004 },
> [TGSI_SEMANTIC_FOG ] = { EMIT_4F, INTERP_PERSPECTIVE, 5, 5, 0x00000010 },
> [TGSI_SEMANTIC_PSIZE ] = { EMIT_1F_PSIZE, INTERP_POS , 6, 6, 0x00000020 },
> - [TGSI_SEMANTIC_GENERIC ] = { EMIT_4F, INTERP_PERSPECTIVE, 8, 7, 0x00004000 }
> + [T...
2015 May 26
2
[PATCH 2/2] nv30/draw: switch varying hookup logic to know about texcoords
...30/nv30_draw.c
>>> index a681135..03c0c70 100644
>>> --- a/src/gallium/drivers/nouveau/nv30/nv30_draw.c
>>> +++ b/src/gallium/drivers/nouveau/nv30/nv30_draw.c
>>> @@ -230,22 +230,24 @@ static const struct {
>>> [TGSI_SEMANTIC_BCOLOR ] = { EMIT_4F, INTERP_LINEAR , 1, 3,
>>> 0x00000004 },
>>> [TGSI_SEMANTIC_FOG ] = { EMIT_4F, INTERP_PERSPECTIVE, 5, 5,
>>> 0x00000010 },
>>> [TGSI_SEMANTIC_PSIZE ] = { EMIT_1F_PSIZE, INTERP_POS , 6, 6,
>>> 0x00000020 },
>>> - [TGSI_SEMANTIC_GENERIC...
2015 May 25
3
[PATCH 1/2] nv30/draw: rework some of the output vertex buffer logic
This makes the vertex buffer go to GART, not VRAM, and redoes the
mapping to not use the UNSYNCHRONIZED access (which is meaningless on a
VRAM buffer anyways). While we're at it, add some flushes for VBO data.
Moving the vertex buffer from VRAM to GART makes glxgears work fully
with NV30_SWTNL=1. The other changes just seem like a good idea. I'm not
sure *why* moving the buffer from VRAM
2009 Sep 12
0
[PATCH 10/13] nv50: proper linkage between VP and FP
...switch (d->Declaration.Interpolate) {
case TGSI_INTERPOLATE_CONSTANT:
mode = INTERP_FLAT;
+ flat_nr++;
break;
case TGSI_INTERPOLATE_PERSPECTIVE:
mode = INTERP_PERSPECTIVE;
+ p->cfg.regs[1] |= 0x08 << 24;
break;
default:
mode = INTERP_LINEAR;
break;
}
-
- if (d->Declaration.Semantic) {
- switch (d->Semantic.SemanticName) {
- case TGSI_SEMANTIC_POSITION:
- fcrd = first;
- break;
- case TGSI_SEMANTIC_COLOR:
- fcol = first;
- mode = INTERP_PERSPECTIVE;
- break;
- }
- }
-
-...
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they