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interactiv
2017 Jul 13
2
Deprecating the experimental microMIPS64R6 backend
Hi all,
I plan to deprecate the experimental microMIPS64R6 backend for the 5.0 release
and remove it after the release.
Currently there are no CPUs that use that particular sub-ISA which makes it difficult
to justify the maintenance and parallel development effort.
If there was a CPU design produced that did use microMIPS64R6, the backend could
be restored from the archive.
Any comments or