search for: intel_bridge_1f

...void intel_pch_init(PCIBus *bus) did = pt_pci_host_read(pci_dev_1f, PCI_DEVICE_ID, 2); rid = pt_pci_host_read(pci_dev_1f, PCI_REVISION, 1); - if ( vid == PCI_VENDOR_ID_INTEL ) - pci_bridge_init(bus, PCI_DEVFN(0x1f, 0), vid, did, rid, - pch_map_irq, "intel_bridge_1f"); + if (vid == PCI_VENDOR_ID_INTEL) { + pci_isa_bridge_init(bus, PCI_DEVFN(0x1f, 0), vid, did, rid, + pch_map_irq, "intel_bridge_1f"); + + } } uint32_t igd_read_opregion(struct pt_dev *pci_dev) -- 1.7.10.4

The OpRegion shouldn''t be mapped 1:1 because the address in the host can''t be used in the guest directly. This patch traps read and write access to the opregion of the Intel GPU config space (offset 0xfc). To work correctly this patch needs a change in hvmloader. HVMloader will allocate 2 pages for the OpRegion and write this address on the config space of the Intel GPU. Qemu

This series contains all the fixes required to produce a working IGD passthrough box. All the changes are previously seen in the dev list but not yet accepted. Some of them are out-dated and need some reshape. Detailed description can be found later in each patch. . [PATCH 1/3] qemu-xen-trad/pt_msi_disable: do not clear all MSI flags . [PATCH 2/3] qemu-xen-trad: Correctly expose PCH ISA bridge