Displaying 3 results from an estimated 3 matches for "integernti".
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integernty
2015 Apr 11
2
[LLVMdev] How doesn't llvm generate IR for logical negate operation
Yes, but my point is that there would be some overhead to do cast the <N x
i1> vectortype to an integerNty. Is there any good way to check not all of
these N bits in the vectortype are 0s?
On Fri, Apr 10, 2015 at 5:37 PM, Bruce Hoult <bruce at hoult.org> wrote:
> Sure, if you actually just want an i1 saying whether or not at least one
> bit is set to 1, then comparing against 0
2015 Apr 11
2
[LLVMdev] How doesn't llvm generate IR for logical negate operation
I see. My CPU is a general Core i7 Ivy bridge CPU.
On Fri, Apr 10, 2015 at 6:48 PM, Bruce Hoult <bruce at hoult.org> wrote:
> I suppose that depends on your CPU. Do you even have a CPU that supports
> operations on <N x i1> as packed bits in vector registers?
>
>
> On Sat, Apr 11, 2015 at 12:43 PM, zhi chen <zchenhn at gmail.com> wrote:
>
>> Yes, but my
2015 Apr 11
2
[LLVMdev] How doesn't llvm generate IR for logical negate operation
Thanks, Bruce. So, what is the easiest way to check if there is any bit set
to 1 in a <N x i1> vector type? I used bitcast instruction to cast it into
"iN" first and them compare iN to 0. Do you have a better way to do it?
Thanks again.
On Fri, Apr 10, 2015 at 5:22 PM, Bruce Hoult <bruce at hoult.org> wrote:
> LLVM doesn't have a "logical neg" (or