search for: intb

I fit the model fit<-lm(thresh~cond*Ne) where thresh is the reponse cond is a factor with levels a, b, and c Ne is a continuous indep var I think of this full model as having three lines: thresh as a function of Ne for each condition. Thus we have slopea, slopeb, slopec, inta, intb, intc. lm output my params ------------------------- (Intercept) inta condb intb - inta condc intc - inta Ne slopea condb:Ne slopeb - slopea condc:Ne slopec - slopea This parametrization automatically compares inta vs intb inta vs intc But how to get...

...ffic to the appropriate IP depending on the interface the packet gets routed onto. The setup looks something like this: Interface IP Gateway Table Network --------- -- ------- ----- ------- intA ipA gwA tableA netA intB ipB gwB tableB netB intC ipC gwC tableC netC [intD is the LAN interface] intD ipD (private) no gateway global netD This works fine most of the time, except that once in a while (every 5-10 minutes or so) packets going out on...

...000, size 16, enabled pcib1: allocated prefetch range (0xd50e0000-0xd50effff) for rid 18 of pci0:2:0:1 map[20]: type Prefetchable Memory, range 64, base 0xd50f0000, size 16, enabled pcib1: allocated prefetch range (0xd50f0000-0xd50fffff) for rid 20 of pci0:2:0:1 pcib1: matched entry for 2.0.INTB pcib1: slot 0 INTB hardwired to IRQ 36 bge0: <Broadcom NetXtreme Gigabit Ethernet, ASIC rev. 0x5720000> mem 0xd50a0000-0xd50affff,0xd50b0000-0xd50bffff,0xd50c0000-0xd50cffff irq 34 at device 0.0 on pci2 bge0: APE FW version: NCSI v1.0.80.0 bge0: attempting to allocate 1 MSI vectors (8 support...

I have a problem with an SMP 4.7 kernel with ichsmb. My BIOS has not assigned an interrupt, so the kernel does on startup: ichsmb0: <Intel 82801CA (ICH3) SMBus controller> port 0x1100-0x111f irq 0 at device 31.3 on pci0 pci_cfgintr_virgin: using routable interrupt 3 pci_cfgintr: 0:31 INTB routed to irq 3 smbus0: <System Management Bus> on ichsmb0 smb0: <SMBus general purpose I/O> on smbus0 however, I don't seem to ever get an interrupt to the ichsmb driver. I'm suspicious of the choice of irq 3 above, that's the edge interrupt for the serial port, not a lev...

...9;s assertion: llc: LiveIntervals.cpp:507: void llvm::LiveIntervals::joinIntervals(): Assertion `rcA == rcB && "registers must be of the same class"' failed. (gdb) up 4 ..... (gdb) p *intA $1 = (llvm::LiveInterval &) @0x8064698: {reg = 1030, weight = 0, ........ (gdb) p *intB $2 = (llvm::LiveInterval &) @0x80646b8: {reg = 1031, weight = 0, ....... Is there anything I can do to make it work? Actually, it seems like a bug in register allocator. If it can't coalesce intervals because there are different register classes, it should just leave the move alone, not...

On Jan 31, 2008, at 5:05 AM, Roman Levenstein wrote: > Hi, > > I'm trying to sketch an LLVM-based implementation of the Extended > Linear Scan algorithm, described in this Vivek Sarkar's paper: > http://www.cs.rice.edu/~vs3/PDF/cc2007.pdf > Sarkar reports that this version of Linear Scan produces better code > than graph-coloring regallocs and is also much faster (15x

Thomas, Have spoken to Soren, from my bootlog he believes that the problem is in atapicam causing the system to lock up. He is happy to answer some questions but doesnt have time to delve into atapicam himself. Did you author atapicam, I have seen your name on the sourcecode, can you help me further? Whats next? Thanks Adam. -------------- next part -------------- An embedded message was

...x66 on acpi0 acpi_acad0: <AC Adapter> on acpi0 battery0: <ACPI Control Method Battery> on acpi0 acpi_lid0: <Control Method Lid Switch> on acpi0 acpi_button0: <Sleep Button> on acpi0 pcib0: <ACPI Host-PCI bridge> port 0xcf8-0xcff on acpi0 pci_link3: BIOS IRQ 11 for 0.29.INTB is invalid pci0: <ACPI PCI bus> on pcib0 agp0: <Intel 82855 host to AGP bridge> on hostb0 pcib1: <ACPI PCI-PCI bridge> at device 1.0 on pci0 pci1: <ACPI PCI bus> on pcib1 vgapci0: <VGA-compatible display> port 0x3000-0x30ff mem 0xd8000000-0xdfffffff,0xd0100000-0xd010f...

...ap[20]: type I/O Port, range 32, base 0xf000, size 5, enabled pcib0: allocated type 4 (0xf000-0xf01f) for rid 20 of pci0:0:31:2 map[24]: type Memory, range 32, base 0xf7c22000, size 11, enabled pcib0: allocated type 3 (0xf7c22000-0xf7c227ff) for rid 24 of pci0:0:31:2 pcib0: matched entry for 0.31.INTB pcib0: slot 31 INTB hardwired to IRQ 19 found-> vendor=0x8086, dev=0x1c22, revid=0x05 domain=0, bus=0, slot=31, func=3 class=0c-05-00, hdrtype=0x00, mfdev=0 cmdreg=0x0143, statreg=0x0280, cachelnsz=0 (dwords) lattimer=0x00 (0 ns), mingnt=0x00 (0 ns), maxlat=0x00 (0 ns) intpin=c, irq=5 map[...

Hi, I'm trying to sketch an LLVM-based implementation of the Extended Linear Scan algorithm, described in this Vivek Sarkar's paper: http://www.cs.rice.edu/~vs3/PDF/cc2007.pdf Sarkar reports that this version of Linear Scan produces better code than graph-coloring regallocs and is also much faster (15x to 68x). I already started work on the implementation of this algorithm and have a few

Thanks Nick. I've been pursuing Gao's technique but can't seem to get opt to remove obviously dead code from even the following trivial example: int mult(int a, int b){ return a*b; } int main(void){ return 0; } While mult is never called it still is not removed. I just can't seem to get opt to understand it's seeing the whole program so it can remove this

Hi there, I'm having some fairly serious asterisk problems, which seem to be spread quite liberally across all asterisk versions, I've tried 1.4.2, 1.6.0.10, 1.6.2beta4 and still had exactly the same problem with static and echo on the line when using the PRI interface. A little background: Server: HP DL145 G3 Dual Opteron 246 with 2GB ram and a brand new OpenVox D110P

...=0x0117, statreg=0x02a0, cachelnsz=16 (dwords) lattimer=0x20 (960 ns), mingnt=0x00 (0 ns), maxlat=0x00 (0 ns) intpin=b, irq=10 map[10]: type Memory, range 32, base 0xfe9fd000, size 12, enabled pcib0: allocated type 3 (0xfe9fd000-0xfe9fdfff) for rid 10 of pci0:0:19:1 pcib0: matched entry for 0.19.INTB pcib0: slot 19 INTB hardwired to IRQ 17 ohci early: SMM active, request owner change found-> vendor=0x1002, dev=0x4389, revid=0x00 domain=0, bus=0, slot=19, func=2 class=0c-03-10, hdrtype=0x00, mfdev=0 cmdreg=0x0117, statreg=0x02a0, cachelnsz=16 (dwords) lattimer=0x20 (960 ns), mingnt=0x00 (...

...(0x3060-0x307f) for rid 20 of pci0:0:31:2 Sep 20 15:40:31 rmbp kernel: map[24]: type Memory, range 32, base 0xc1c16000, size 11, enabled Sep 20 15:40:31 rmbp kernel: pcib0: allocated type 3 (0xc1c16000-0xc1c167ff) for rid 24 of pci0:0:31:2 Sep 20 15:40:31 rmbp kernel: pcib0: matched entry for 0.31.INTB Sep 20 15:40:31 rmbp kernel: pcib0: slot 31 INTB hardwired to IRQ 19 Sep 20 15:40:31 rmbp kernel: found-> vendor=0x8086, dev=0x1e22, revid=0x04 Sep 20 15:40:31 rmbp kernel: domain=0, bus=0, slot=31, func=3 Sep 20 15:40:31 rmbp kernel: class=0c-05-00, hdrtype=0x00, mfdev=0 Sep 20 15:40:31 rmbp ke...

...uted irq 11 pci_cfgintr: 2:11 INTA routed to irq 11 pcic0: <Toshiba ToPIC100 PCI-CardBus Bridge> irq 11 at device 11.0 on pci2 pcic0: PCI Memory allocated: 0x88000000 pccard0: <PC Card 16-bit bus (classic)> on pcic0 pci_cfgintr_linked: linked (61) to hard-routed irq 11 pci_cfgintr: 2:11 INTB routed to irq 11 pcic1: <Toshiba ToPIC100 PCI-CardBus Bridge> irq 11 at device 11.1 on pci2 pcic1: PCI Memory allocated: 0x88001000 pccard1: <PC Card 16-bit bus (classic)> on pcic1 isab0: <PCI to ISA bridge (vendor=8086 device=248c)> at device 31.0 on pci0 isa0: <ISA bus> on...

I''m afraid this series is rather a grab bag and it is distressingly large at this stage. With this series I can boot an Xgene board until it fails to find its SATA controller. This is a dom0 issue for which patches are pending from APM (/me nudges Anup). As well as the APM specific platform stuff there are also some generic improvements which were either necessary or useful during this

George has release acked all of these. Otherwise mostly minor updates this time around. Summary: A == acked, M == modified A xen: arm64: Add 8250 earlyprintk support A xen: arm64: Add Basic Platform support for APM X-Gene Storm. A xen: arm64: Add APM implementor id to processor implementers. M xen: arm: add a quirk to handle platforms with unusual GIC layout A xen: arm: allow platform

*RESEND* due to exceeding the mailinglists limit for attachment size. Hi, I''m trying to get secondary vga-passthrough on a HVM guest to work with a AMD HD6570 and the native kernel radeon driver and kernel modesetting. So the guest still gets the emulated stdvga or cirrus device(used in my case here) as primary/boot vga adapter. - When i don''t passthrough the radeon card, the