Displaying 2 results from an estimated 2 matches for "int_x86_sse41_blendvps".
2011 Mar 10
0
[LLVMdev] Vector select/compare support in LLVM
Hey,
I am currently forced to create the BLENDVPS intrinsic as an external
call (via Intrinsic::x86_sse41_blendvps) which has the following
signature (from IntrinsicsX86.td):
def int_x86_sse41_blendvps :
GCCBuiltin<"__builtin_ia32_blendvps">,
Intrinsic<[llvm_v4f32_ty],[llvm_v4f32_ty, llvm_v4f32_ty,
llvm_v4f32_ty],[IntrNoMem]>
Thus, it expects the mask (first operand if i recall correctly) to be a
<4 x float>.
It would be great to have this mirrored in the IR, meanin...
2011 Mar 10
2
[LLVMdev] Vector select/compare support in LLVM
After I implemented a new type of legalization (the packing of i1 vectors), I found that x86 does not have a way to load packed masks into SSE registers. So, I guess that legalizing of <4 x i1> to <4 x i32> is the way to go.
Cheers,
Nadav
-----Original Message-----
From: Rotem, Nadav
Sent: Thursday, March 10, 2011 11:04
To: 'David A. Greene'
Cc: llvmdev at cs.uiuc.edu