Displaying 5 results from an estimated 5 matches for "int_x86_".
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
Here's a couple examples for mapping an intrinsic to an X86 instruction
from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
let Pre...
2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...helped too, but read the above page first:
https://llvm.org/docs/TableGen/LangRef.html
On Sun, Mar 18, 2018 at 7:43 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> Here's a couple examples for mapping an intrinsic to an X86 instruction
> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
> find others.
>
> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
> IIC_S...
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...page first:
> https://llvm.org/docs/TableGen/LangRef.html
>
> On Sun, Mar 18, 2018 at 7:43 PM, Craig Topper <craig.topper at gmail.com>
> wrote:
>
>> Here's a couple examples for mapping an intrinsic to an X86 instruction
>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
>> find others.
>>
>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
>>...
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
.../llvm.org/docs/TableGen/LangRef.html
>>
>> On Sun, Mar 18, 2018 at 7:43 PM, Craig Topper <craig.topper at gmail.com>
>> wrote:
>>
>>> Here's a couple examples for mapping an intrinsic to an X86 instruction
>>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can
>>> find others.
>>>
>>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
>>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
>>> "clflushopt\t$src", [(int_x86_clflushopt ad...