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int_riscv_read_cycle
2015 Jan 11
2
[LLVMdev] Backend Tablegen Instruction Definition
All, in working through the RISCV LLVM backend, I’m running into some trouble in defining the instruction formats for the system instruction. The system instructions follow a pre-defined instruction template (type-I), but differ in that they have no input registers (only the target). The system instructions are defined as:
rdcycle Rt
I’ve defined a stand-alone instruction definition (as