search for: insttest

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2012 Apr 07
3
[LLVMdev] Problems on getting the OPT resultant bitcode
Hi, I want to write a piece of code to instrument c++ programs. I have finished writing the pass, but I do not know how to get the resultant bitcode I ran OPT with the following arguments: opt -basiccg -basicaa -load /home/andy/llvm-3.0.src/Release/lib/InstTest.so -InstTest </home/andy/llvm-3.0.src/workspace/threadTest/Debug/threadTest.bc> -o=</home/andy/output/out.bc> /dev/null where </home/andy/llvm-3.0.src/workspace/threadTest/Debug/threadTest.bc> is the input file, and </home/andy/output/out.bc> is the expected output file. Ins...
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST: InstrItinClass; def ALU1: ProcResource<1>; def ALU2: ProcResource<1>; def WriteALU1: SchedWriteRes&...