Displaying 6 results from an estimated 6 matches for "instsp".
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2011 Nov 08
0
[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?
...list<dag> pattern> : F3<outs, ins, asmstr,
pattern> {
bits<13> simm13;
let op = opVal;
let op3 = op3val;
let Inst{13} = 1; // i field = 1
let Inst{12-0} = simm13;
}
class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSP<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<6> op3;
bits<5> rs1;
let op{1} = 1; // Op = 2 or 3
let Inst{29-25} = rd;
let Inst{24-19} = op3;
let Inst{18-14} = rs1;
}
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instructio...
2011 Jan 08
0
[LLVMdev] Unreachable executed with fast Regalloc and Sparc backend
...s is related to this entry in SparcInstrInfo.td:
let Uses = [O0, O1, O2, O3, O4, O5],
hasDelaySlot = 1, isCall = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
def CALL : InstSP<(outs), (ins calltarget:$dst),
"call $dst", []> {
bits<30> disp;
let op = 1;
let Inst{29-0} = disp;
}
The Uses=[O0,O1,O2,O3,O4,O5] is causing this crash (and similar crashes in the PQBP and Greedy allocators if I remember...
2011 Jan 07
2
[LLVMdev] Unreachable executed with fast Regalloc and Sparc backend
Hello,
When I run LLC with option "-O0 -march=sparc" on following testcase,
fast register allocator crashes with "UNREACHABLE executed" error. LLC
generates code successfully with other standard register allocators
available.
$ cat call.ll
define void @test() nounwind {
entry:
%0 = tail call i32 (...)* @foo() nounwind
tail call void (...)* @bar() nounwind
ret void
}
2011 Jan 22
3
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Hello all,
I am adding a new target into LLVM. However there is a assembler for that
target and I just want LLVM to generate assembly. I read the document
"Writing an LLVM Backend". I am wondering to know whether I can ignore the
Inst field in the following example:
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {
field bits<32> Inst;
let Namespace = "SP";
bits<2> op;
let Inst{31-30} = op;
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
}...
2011 Dec 02
0
[LLVMdev] Error: Type constraint application shouldn't fail!
...),
(ncmul
(sext (i16 (extractelt node:$a, (i32
1)))),
(sext (i16 (extractelt node:$b, (i32
0))))
)
)
>;
def ADDMULv : InstSP< (outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
"muladd $a, $b, $dst",
[(set (i32 IntRegs:$dst), (mula_pat (v2i16
IntRegs:$a), (v2i16 IntRegs:$b)))]>;
IntRegs is class with a type list of [i32, v2i16]
But I get the following error when...
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
Hi,
I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing).
I'm basing the code on the PowerPC version, which itself is based on the X86 version.
This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close.
However, the PowerPC