search for: instselect

...uot; the LLVM IR to machine code >> instructions. > > The part of the code generator that converts LLVM IR to machine code IR is > called the 'instruction selection' phase. You can find some documentation > for it here: > http://llvm.cs.uiuc.edu/docs/CodeGenerator.html#instselect > > Unfortunately the code generator is not as well documented as it should be > (though this is slowly improving). The best way to see how this process > works is to look at example instructions. Most of the code for lowering > standard instructions is held in > lib/CodeGen/Sel...

...is used to "parser" the LLVM IR to machine code > instructions. The part of the code generator that converts LLVM IR to machine code IR is called the 'instruction selection' phase. You can find some documentation for it here: http://llvm.cs.uiuc.edu/docs/CodeGenerator.html#instselect Unfortunately the code generator is not as well documented as it should be (though this is slowly improving). The best way to see how this process works is to look at example instructions. Most of the code for lowering standard instructions is held in lib/CodeGen/SelectionDAG/SelectionDAGISe...

Hi: I have extended the IR for adding flag. But I just want this flag to pass through the backend machine code. I know there're several passes like register relocation, schedualing, etc. But I think I just miss the part which is used to "parser" the LLVM IR to machine code instructions. Would you give me some help? Thank you ! > On Sun, 10 Jul 2005 shding at mtu.edu wrote:

...oessenkool wrote: >> a new instruction selection framework, > > Hi Chris, > > Any documentation on that insn selection framework? Or just > point me to the source files ;-) There is not enough, but a high level overview is here: http://llvm.cs.uiuc.edu/docs/CodeGenerator.html#instselect The best way is to learn by example, e.g. take a look at Target/PowerPC/PPC32ISelPattern.cpp. The primary header files are in include/llvm/CodeGen/SelectionDAG*.h Hope this helps, if you have any questions, llvmdev is a good place to go for help. -Chris -- http://nondot.org/sabre/ http://ll...

...h one size of integer registers), expanding integers (e.g. 64-bit integers into two 32-bit registers), etc. Currently, the Alpha, IA-64, and X86 backends use this framework. There is some high-level documentation available here: http://llvm.cs.uiuc.edu/docs/CodeGenerator.html#instselect 17. Reid enhanced the X86 backend to emit Cygwin-compatible .s files. 18. The tblgen backend that autogenerates target-specific asm writers generates much more compact and efficient asmwriters. This works around the "g++ hits swap compiling asmwriters in optimized builds"...