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...s space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at http://www.tilera.com/scm/docs/index.html. the attached patches contains the following main features for tilegx backend: 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Basic support for Asm Parser. 5. MC Layer (aware of VLIW), MCJIT support. I've run the regression test and standalone test-suite natively on TILE-Gx silicon. The test results are: regression --- Expected Passes : 13218 Expected Failures : 78 Unsupported Tests : 68 Unexpe...

Hi Chris, could you please comment on committing TILE-Gx backend into community? ========== TILE-Gx Status =========== Features Supported === 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Asm Parser 5. MC Layer (aware of instruction bundle), MCJIT support. 6. Initial regression tests for CodeGen & MC Layer. Regression Result === Expected Passes : 13363 Expected Failures : 84 Unsupported Tests : 76 Unexpected Failures: 21 20 of the unexpected failures are...

...t;> More information on the architectures is available at >> http://www.tilera.com/scm/docs/index.html. >> >> the attached patches contains the following main features for tilegx >> backend: >> >> 1. general function. >> 2. PIC/TLS/JumpTable. >> 3. Instructoin Bundling for VLIW. >> 4. Basic support for Asm Parser. >> 5. MC Layer (aware of VLIW), MCJIT support. >> >> I've run the regression test and standalone test-suite natively on >> TILE-Gx silicon. The >> test results are: >> >> regression >> -...

...-store architecture ISAs. > > More information on the architectures is available at > http://www.tilera.com/scm/docs/index.html. > > the attached patches contains the following main features for tilegx > backend: > > 1. general function. > 2. PIC/TLS/JumpTable. > 3. Instructoin Bundling for VLIW. > 4. Basic support for Asm Parser. > 5. MC Layer (aware of VLIW), MCJIT support. > > I've run the regression test and standalone test-suite natively on > TILE-Gx silicon. The > test results are: > > regression > --- > Expected Passes : 13218 &g...

...nds like the general functionality level is high enough. Taking it into mainline sounds great, so long as it is reviewed by someone. -Chris > > > ========== TILE-Gx Status =========== > > Features Supported > === > 1. general function. > 2. PIC/TLS/JumpTable. > 3. Instructoin Bundling for VLIW. > 4. Asm Parser > 5. MC Layer (aware of instruction bundle), MCJIT support. > 6. Initial regression tests for CodeGen & MC Layer. > > Regression Result > === > Expected Passes : 13363 > Expected Failures : 84 > Unsupported Tests : 76 > Unexpecte...

...store architecture ISAs. > > More information on the architectures is available at > http://www.tilera.com/scm/docs/index.html . > > the attached patches contains the following main features for tilegx > backend: > > 1. general function. > 2. PIC/TLS/JumpTable. > 3. Instructoin Bundling for VLIW. > 4. Basic support for Asm Parser. > 5. MC Layer (aware of VLIW), MCJIT support. > > I've run the regression test and standalone test-suite natively on > TILE-Gx silicon. The > test results are: > > regression > --- > Expected Passes : 13218 &g...

...a VLIW architecture with 64-bit registers, 64-bit address space, and 64-bit instructions. TILE-Gx has load-store architecture ISAs. More information on the architectures is available at http://www.tilera.com/scm/docs/index.html. features supported --- 1. general function. 2. PIC/TLS/JumpTable. 3. Instructoin Bundling for VLIW. 4. Asm Parser (no support for bundle syntax .s, need modification on generic MC code to support this) 5. MC Layer (support instruction bundle), MCJIT support. regression result --- Expected Passes : 13318 Expected Failures : 78 Unsupported Tests : 68 Unexpected Failures: 32 (20...

On 03/02/2013 04:50 AM, Dmitri Gribenko wrote: > You also need tests for Clang bits, too. > > Mechanical issues: > > +/// getTileRegisterNumbering - Given the enum value for some register, > +/// return the number that it corresponds to. > > Please don't duplicate function and class name in comments. Existing > code does this, but current style guidelines advise not

...;> More information on the architectures is available at >> http://www.tilera.com/scm/docs/index.html . >> >> the attached patches contains the following main features for tilegx >> backend: >> >> 1. general function. >> 2. PIC/TLS/JumpTable. >> 3. Instructoin Bundling for VLIW. >> 4. Basic support for Asm Parser. >> 5. MC Layer (aware of VLIW), MCJIT support. >> >> I've run the regression test and standalone test-suite natively on >> TILE-Gx silicon. The >> test results are: >> >> regression >> -...

.../HowToAddABuilder.html to setup a TILE-Gx buildbot. --- Regards, Jiong Tilera Corporation. > > -Chris > > >> >> ========== TILE-Gx Status =========== >> >> Features Supported >> === >> 1. general function. >> 2. PIC/TLS/JumpTable. >> 3. Instructoin Bundling for VLIW. >> 4. Asm Parser >> 5. MC Layer (aware of instruction bundle), MCJIT support. >> 6. Initial regression tests for CodeGen & MC Layer. >> >> Regression Result >> === >> Expected Passes : 13363 >> Expected Failures : 84 >> Un...