Displaying 3 results from an estimated 3 matches for "instructionselectionbasicblock".
2007 Sep 30
2
[LLVMdev] Q about instruction pattern matching
...st work.
>
>
> Also, I'm uncertain as to how this custom DR->AR op replacer pass fits
> into this whole soup and where it is supposed to happen, as I'm still
> pretty clueless with llvm internals. :)
It should happen right after selection and before scheduling (i.e. in
InstructionSelectionBasicBlock before it calls ScheduleAndEmitDAG). I
would suggest you focusing on getting this down before you start
worrying about the downstream passes.
Evan
>
>
> Thanks,
> Andreas
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2007 Sep 29
0
[LLVMdev] Q about instruction pattern matching
On 9/25/07, Evan Cheng <evan.cheng at apple.com> wrote:
> > Hi Evan,
> > wouldn't this generate fairly terrible code if each address register
> > use has to be preceded by instructions to make an address register
> > hold the right value?
>
> No. I would suggest doing this as a instruction selection post pass.
> It would operate on DAGs so you still get
2007 Sep 25
2
[LLVMdev] Q about instruction pattern matching
On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote:
> On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote:
>
>> I am going to suggest something shocking. :) Since you will end up
>> writing a
>> bunch of target specific code anyway, you might a well write a target
>> specific pass that change generic instructions into data register
>> variant