search for: instructionselect

...? > Basically, I'd have to do more experiments to figure that one out. > > As far as where time is spent in the gisel-passes itself, on average, I saw the following on the latest CTMark experiment I ran: > Avg compile time spent in IRTranslator: 4.61% > Avg compile time spent in InstructionSelect: 7.51% > Avg compile time spent in Legalizer: 1.06% > Avg compile time spent in Localizer: 0.76% > Avg compile time spent in RegBankSelect: 2.12% > >> >>> * My usual performance benchmarking run: 8.5% slow-down. This was about 9.5% before the Localizer pass landed, so a...

...t; Basically, I'd have to do more experiments to figure that one out. > > As far as where time is spent in the gisel-passes itself, on average, I > saw the following on the latest CTMark experiment I ran: > Avg compile time spent in IRTranslator: 4.61% > Avg compile time spent in InstructionSelect: 7.51% > Avg compile time spent in Legalizer: 1.06% > Avg compile time spent in Localizer: 0.76% > Avg compile time spent in RegBankSelect: 2.12% > > > * My usual performance benchmarking run: 8.5% slow-down. This was about > 9.5% before the Localizer pass landed, so a slight i...

...ombiner, and how much work this will be to implement, I think the fastest path to doing this would be to run some of the GlobalISel passes after SelectionDAG instruction selection. What I would like to do is modify the AMDGPU target to select SelectionDAG nodes to generic opcodes, and then run the InstructionSelector pass on the resulting MachineFunction. I would start by doing this with loads/stores and then move on to other opcodes one at a time. These changes will be a big improvement to AMDGPU, because it will allow us to replace our SIFixSGPRCopies pass which is essentially just another instruction sel...

...happening? Alternatively if you can point me to the biggest offender, I can have a look. The only thing I can think of is that we duplicate constants that are expensive to materialize. If that’s the case, we were discussing with Ahmed an alternative to the localizer pass that would operate during InstructionSelect so may be worth pursuing. > * Debug info quality: I didn't do another recheck, trusting that the Localizer pass wouldn't change debug info quality. > * Stack size usage: I don't know of a good way to measure this, but Diana's experiments show that at least for bootstrapping i...

...d have to do more experiments to figure that one out. >> >> As far as where time is spent in the gisel-passes itself, on average, I >> saw the following on the latest CTMark experiment I ran: >> Avg compile time spent in IRTranslator: 4.61% >> Avg compile time spent in InstructionSelect: 7.51% >> Avg compile time spent in Legalizer: 1.06% >> Avg compile time spent in Localizer: 0.76% >> Avg compile time spent in RegBankSelect: 2.12% >> >> >> * My usual performance benchmarking run: 8.5% slow-down. This was about >> 9.5% before the Localize...

...T. 8) error: ‘class llvm::SDValue’ has no member named ‘Val’ SDOperand had 'Val' which can be replaced by getNode(). 9) switch(op.getOperand(1).getValueType()) does not work In our case I could replace it with switch(op.getOperand(1).getValueType().getSimpleVT()) 10) SelectionDAGIsel::InstructionSelectBasicBlock removed Replaced with InstructionSelect() 11) no matching function for call to llvm::AsmPrinter::AsmPrinter(std::basic_ostream<char, std::char_traits<char>... The stream argument has been changed to llvm::raw_ostream Also had to change std::endls to '\n' i...

In the 2.3 release, we included a list of the major LLVM API changes. If you are working on upgrading your code from 2.3 to 2.4, I'd appreciate it if you could compile a list of the major stumbling blocks you have, so that others can benefit from your experience. Please send any info to the list, thanks! -Chris

...nkSelect ** - Core logic is present, no optimizations yet, or more accurately, the greedy mode is still pretty silly. - TableGen support for RegisterBanks description. * What’s Left * - TableGen the instruction mapping from the existing SDISel patterns. - Improve the optimization heuristic. ** InstructionSelect ** - Core logic present. - TableGen support for simple SDISel patterns (i.e., GISel reuses SDISel patterns) * What’s Left * - Teach TableGen how to reuse more complex patterns: — Patterns with combines in them (e.g., (mull (add)) => madd) — Patterns with complex patterns (e.g., SelectAddressM...

I was under the impression his answer was correct from your reply, no? On Oct 17, 2016 17:45, "Alex Bradley via llvm-dev" <llvm-dev at lists.llvm.org> wrote: > Gentle Ping !! > > I would appreciate any help on this. I want to generate following as > described by Krzysztof : > > %v1 = load i32, i32* %a > %v2 = load i32, i32* %b > %v3 = add i32 %v1, %v2 >

...Yes, inserting explicit patterns everywhere would make a complete mess of my InstrInfo.td. All arithmetic requires D-regs, and all load/stores require P-regs. It would be fairly simple to insert move instructions in the selection DAG after instruction selection is complete. I could do this in my InstructionSelect() as a first fix, but I think I would have to do something more clever eventually. I think a few tricks when creating vregs would go a long way: 1. If the def regclass is a subset of the operand regclass, there is no problem. ScheduleDAGSDNodes::AddOperand should simply allow this case. 2...

...as introduced alongside a new isCopyInstr hook. This support is a pre-requisite for a patch which allows LiveDebugValues to follow a variable's value moving from one register to another. [r333093](https://reviews.llvm.org/rL333093). * A series of patches that aims to improve the performance of InstructionSelect during GlobalISel have started to land. [r332907](https://reviews.llvm.org/rL332907). * The RISC-V backend gained support for tail call optimisation. [r333137](https://reviews.llvm.org/rL333137). * Floating point binary operations with undef operands now fold to NaN. [r332920](https://reviews.llv...

...s. Some target instructions work with specified registers (not all registers in RegisterClass). Often it's one or two registers. I don't understand how use ComplexPattern in this case. But if I don't use ComplexPattern I'll have other problems - not all instruction can select in InstructionSelection pass. My work place here: https://github.com/earl1k/llvm-z80 Example of some load instructions for Z80 CPU with opcode: Opcode Instruction node pattern 0x46 LD $dst,(HL) (set GR8:$dst, (load HL)) 0x0A LD A,(BC) (set A, (load B...

...rywhere would make a complete mess > of my InstrInfo.td. All arithmetic requires D-regs, and all load/ > stores > require P-regs. > > It would be fairly simple to insert move instructions in the selection > DAG after instruction selection is complete. I could do this in my > InstructionSelect() as a first fix, but I think I would have to do > something more clever eventually. > > I think a few tricks when creating vregs would go a long way: > > 1. If the def regclass is a subset of the operand regclass, there is > no > problem. ScheduleDAGSDNodes::AddOperand sh...

On Mar 15, 2009, at 2:02 PM, Jakob Stoklund Olesen wrote: > Hi, > > I am writing a backend for the Blackfin processor from Analog > Devices. I > just started so I still have a lot to learn about the code > generator. So > far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but > that is about it. > > The Blackfin 32-bit registers divide naturally

Hi all, opt and opt + llc generate the difference aarch64 asm code for the following LLVM code. Is it intended behavior? I expected (A) because I cast %p from i192* to i64*. The information is dropped by opt and 8-byte padding is inserted or I write a bad code? % cat a.ll define void @store0_to_p4(i192* %p) { %p1 = bitcast i192* %p to i64* %p2 = getelementptr i64, i64* %p1, i64 3 %p3 =

Hi, I am writing a backend for the Blackfin processor from Analog Devices. I just started so I still have a lot to learn about the code generator. So far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but that is about it. The Blackfin 32-bit registers divide naturally into several classes. I have modelled these register classes without knowing anything about what the code

Cool test :) It seems to work fine now, I don't see any new failures. IIUC, Kristof is also giving it another run. Cheers, Diana On 30 May 2017 at 22:57, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > I’ve actually gone ahead and pushed the fix as I was able to produce a > small reproducer. > > This is r304244 > > Let me know if you encounter