search for: instrucitons

llvm is giving me some assertion errors when trying to replace an instruction, and I'm not quite sure of what to do. I have the following snippet of code: switch((*I)->getOpcode()) { case Instruction::Malloc: { AllocaInst *AI; AI = new AllocaInst(cast<AllocationInst>(*I)->getAllocatedType(), cast<AllocationInst>(*I)->getArraySize());

On Sat, 23 Jun 2012 22:28:55 +0100 Tim Northover <t.p.northover at gmail.com> wrote: > On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > > Working on a target I added this pattern: > > > > def : Pat<(v4i64 (load xoaddr:$src)), > > (QVFCTIDb (QVLFDXb xoaddr:$src))>; > > > > I'd like to fix this so that it works

On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > Working on a target I added this pattern: > > def : Pat<(v4i64 (load xoaddr:$src)), > (QVFCTIDb (QVLFDXb xoaddr:$src))>; > > I'd like to fix this so that it works correctly: the TokenFactor > inputs should be attached to all inner-most instructions. I'm guessing > this is somewhere in

On Sat, 23 Jun 2012 21:18:37 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > On Sat, 23 Jun 2012 22:28:55 +0100 > Tim Northover <t.p.northover at gmail.com> wrote: > > > On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > > > Working on a target I added this pattern: > > > > > > def : Pat<(v4i64 (load xoaddr:$src)), > >

Working on a target I added this pattern: def : Pat<(v4i64 (load xoaddr:$src)), (QVFCTIDb (QVLFDXb xoaddr:$src))>; which represents an actual load followed by a necessary conversion operation. The problem is that when this matches any TokenFactor that was attached to the load node gets attached, not to the inner load instruction, but the outer conversion operation. This is

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

...regression. e_t=sqrt(h_t)*N(0,1) h_t=alpha0+alpha1*e_t^2+beta*h_{t_1}~~~~~~~GARCH(1,1). I didn't know how to estimate the model using function garchFit or garchOxFit or other functions? because the argument in garchFit/garchOxFit is formular.mean=~arma(1,1). Do you have some instrucitons? thank you very much for you help. Best wishes Ma Yuchao [[alternative HTML version deleted]]

Hi, We come across a ScalarEvolution (SE) problem the other day. It seems to be a fundamental design problem. I don't think I have a clean and cheap fix to this problem. I talked with Andy in the phone yesterday, he told me it is a known fundamental problem. But I don't see any discussion on this problem on the list, so I post the problem here, soliciting your insightful comment.

On Sun, 1 Oct 2006, Roman Levenstein wrote: > I'm trying to implement a new backend for an embedded CISC processor. > Therefore I thought that it makes sense to take X86 target as a basis, > to save some time. Ok. Note that the X86 backend is one of the most complex though, because it supports several subtargets and ABIs, which makes it more complex than some other targets. >

On Sat, 23 Jun 2012 21:25:48 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > On Sat, 23 Jun 2012 21:18:37 -0500 > Hal Finkel <hfinkel at anl.gov> wrote: > > > On Sat, 23 Jun 2012 22:28:55 +0100 > > Tim Northover <t.p.northover at gmail.com> wrote: > > > > > On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > > > >

...only considers only the first possible tree that can be > built from connected pairs for each remaining candidate pair. This is > important for the following reason: If a block of N instructions had the > maximum number of candidate pairs: N*(N-1)/2, then it must be the case > that all instrucitons are independent, and, thus, none of them are > connected. Thus, in this regime, the algorithm is O(N^2). On the other > extreme, if the block has N candidate pairs, then they could all be > connected, but then there are only N of them. In this extreme, the > algorithm is also O(N^2). Be...

...t I am trying to achieve: I want ilex to respond to any incoming trafic on 80.72.34.162 address (it is running a DNS server). All outgoing trafic from localnet should go through tpsa link (faster but non-static IP). Resposnses to the latter should also return through tpsa link. I have followed instrucitons from LARTC howto, chapter 4.2 but to no avail. 3. The problem: after running: ip route del default ip route add default via 213.25.2.3 localnet traffic flows fine, BUT ilex no longer responds to pings from salix on 80.72.34.162 address this happens also in the opposite direction, after runnin...

Hi Chris, Thanks a lot for your answer! Chris Lattner wrote: >> 1. Why does X86 instruction set description provide different >> descriptions for the same instructions, which differ only in the size >> of operands? >> E.g. >> >> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), >> "mov{b} {$src, $dst|$dst, $src}",

...O(N^4). However, it only considers only the first possible tree that can be built from connected pairs for each remaining candidate pair. This is important for the following reason: If a block of N instructions had the maximum number of candidate pairs: N*(N-1)/2, then it must be the case that all instrucitons are independent, and, thus, none of them are connected. Thus, in this regime, the algorithm is O(N^2). On the other extreme, if the block has N candidate pairs, then they could all be connected, but then there are only N of them. In this extreme, the algorithm is also O(N^2). Because both extremes...

Even if I turn to -O0 [in other words, no optimisation passes at all], it takes the same amount of time. The time is spent in 12.94% lacsap lacsap [.] llvm::SDNode::use_iterator::operator== 7.68% lacsap lacsap [.] llvm::SDNode::use_iterator::operator* 7.53% lacsap lacsap [.] llvm::SelectionDAG::ReplaceAllUsesOfValueWith 7.28% lacsap

...I can use "-target" option to specify the androideabi target and by that clang was made to search for the assembler with that target as prefix which actually was not present under /usr/bin by default. Hence, it took the host x86_64 GNU assembler and was complaining about unknown assembly instrucitons. So, I created the necessary symlinks over there pointing to that of Android NDK r13b binutils binaries - this fixed the issue of picking the right assembler. By the way, I saw some reports on successful ARM64/AARCH64 clang-kernel for Google Pixel* but the steps therein didn't work for my ARM(3...

On 11/23/2011 05:52 PM, Hal Finkel wrote: > On Mon, 2011-11-21 at 21:22 -0600, Hal Finkel wrote: >> > On Mon, 2011-11-21 at 11:55 -0600, Hal Finkel wrote: >>> > > Tobias, >>> > > >>> > > I've attached an updated patch. It contains a few bug fixes and many >>> > > (refactoring and coding-convention) changes inspired