search for: instrmap

...ed under lib/Target/X86. A new pass is to be added at the pre-emit stage. It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in: lib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Ta...

...So, in our example of 'ADD', we can have another transformation like this - ADD--- ---> ADDtrue -----> ADDtru_new (predicate new form of true) \-----> ADDfalse -----> ADDfalse_new (predicate new form of false) // Define Predicate New relation def getPredNewOpcode : InstrMapping { let FilterClass = "PredNewRel"; let RowFields = ["BaseOpcode"]; // ColFields is a list of flags/attributes of the instructions. let ColFields = ["DotNewType", "PredSense"]; // Here 'DotNewType' of the KeyCol is "" and Predsen...

...s say that we have three formats for 'ADD' instruction and we want to relate them. ADD - non-predicated form ADD_pt : predicate true ADD_pf : predicate false We can define the relationship between the non-predicated instructions and their predicate formats as follows: def getPredOpcode : InstrMapping { // InstrMapping is a new class defined in Target.td // Used to filter instructions that have this kind of relationship let FilterClass = "PredRel"; // Instructions with the same BaseOpcode value form a row. let RowFields = ["BaseOpcode"]; // Instructions with the same p...

...t_rr : IFormat<1>; def Format_ri : IFormat<2>; def Format_predt : IFormat<3>; def Format_predf : IFormat<4>; Addrr : { Addrr, Addri, Addrr_pt, Addrr_pf, .. , ..} Addri : { Addrr, Addri, Addri_pt, Addri_pf,.. > Do something like this: > > def getPredicatedOpcode : InstrMapping { > // Only include instructions form the PredRel class. > let FilterClass = "PredRel"; > > // Instructions with the same BaseOpcode field form a row. > let RowFields = ["BaseOpcode"]; > > // Instructions with the same predicate sense form a...

Hi, I've spent some time playing around with GlobalISel on the AMDGPU target, and I was wondering if there is any reason to have RegisterBankInfo::getInstrAlternativeMappings() and RegisterBankInfo::getInstrMapping() as separate functions. Could we instead replace these two functions with just one: RegisterBankInfo::getInstrMappings() and then just treat the first mapping in the list as the 'default' mapping to use for 'Fast' RegBankSelect mode? The reason this would make sense (at least...

...tween instructions. I define > multiple IFormat objects one per relationship which finally translates into > a unique column into the mapping table. My point is that you don't need to define additional structure when you can just use the record fields. >> def getPredicatedOpcode : InstrMapping { >> // Only include instructions form the PredRel class. >> let FilterClass = "PredRel"; >> >> // Instructions with the same BaseOpcode field form a row. >> let RowFields = ["BaseOpcode"]; >> >> // Instructions with the same...

...;, we can have > another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new (predicate new form of true) > \-----> ADDfalse -----> ADDfalse_new (predicate new form of false) > > // Define Predicate New relation > def getPredNewOpcode : InstrMapping { > let FilterClass = "PredNewRel"; > > let RowFields = ["BaseOpcode"]; > > // ColFields is a list of flags/attributes of the instructions. > let ColFields = ["DotNewType", "PredSense"]; > > // Here 'DotNewType' of th...

.... You simply use the existing fields in your instructions, or add new ones as needed. You don't want to be limited to a single 'IFormat' as a column identifier, there can be many different types of relationships between instructions. Do something like this: def getPredicatedOpcode : InstrMapping { // Only include instructions form the PredRel class. let FilterClass = "PredRel"; // Instructions with the same BaseOpcode field form a row. let RowFields = ["BaseOpcode"]; // Instructions with the same predicate sense form a column. let ColFields = ["P...

...> can have another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new (predicate new form of true) > \-----> ADDfalse -----> ADDfalse_new (predicate new form of > false) > > // Define Predicate New relation > def getPredNewOpcode : InstrMapping { > let FilterClass = "PredNewRel"; > > let RowFields = ["BaseOpcode"]; > > // ColFields is a list of flags/attributes of the instructions. > let ColFields = ["DotNewType", "PredSense"]; > > // Here 'DotNewType' of th...

Hello LLVM, My target has a complex relaxation hierarchy. Perhaps a modest TableGen extension would help consolidate most of the work involved in choosing a relaxed opcode. I also notice the x86 relaxation code with a comment wondering if TableGen could improve life. Does the following outline sound interesting? 1) Add a new field of type 'Instruction' to the Instruction class called

For example, given a multiclass for ADD 32 bit that might produce something like: ADD32_REG_REG_REG (operands are all registers for a 32 bit add) ADD32_REG_IMM_REG (srcA is a register, srcB is an immediate and dst is a register) ADD32_REG_IMM_MEM (srcA is a register, srcB is an immediate and dst is a memory address) What I'd like to do is replace an operand, for example, change srcA from a

Jyotsna, I hadn't been following this, so I apologize if this has already been provided, but can you give a quick example of how this functionality is used? Thanks in advance, Hal On Tue, 28 Aug 2012 13:01:17 -0500 "Jyotsna Verma" <jverma at codeaurora.org> wrote: > Hi Jakob, > > Here is the first draft of the patch to add TableGen backend support > for the

Hi All. This is an RFC for a proposed target specific X86 optimization for reducing code size in the encoding of AVX-512 instructions when possible. When the AVX512F instruction set was introduced in X86 it included additional 32 registers of 512bit size each ZMM0 - ZMM31, as well as additional 16 XMM registers XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of

...A new pass is to be added at the pre-emit stage. > > It might be better to have TableGen generate the mapping table for you > instead of manually making a table yourself. TableGen has a feature that is > specifically designed to make mapping tables like this. For examples, grep > for InstrMapping in: > > lib/Target/Hexagon/Hexagon.td > lib/Target/Mips/MipsDSPInstrFormats.td > lib/Target/Mips/MipsInstrFormats.td > lib/Target/Mips/Mips32r6InstrFormats.td > lib/Target/PowerPC/PPC.td > lib/Target/AMDGPU/SIInstrInfo.td > lib/Target/AMDGPU/R600Instructions.td > lib/...

Hi Everyone, After some more thoughts to the Jacob's suggestion of using multiclasses for Opcode mapping, this is what I have come up with. Please take a look at the design below and let me know if you have any suggestions/questions. I have tried to keep the design target independent so that other targets could benefit from it. 1) The idea is to add 3 new classes into

...> can have another transformation like this - > > ADD--- ---> ADDtrue -----> ADDtru_new (predicate new form of true) > \-----> ADDfalse -----> ADDfalse_new (predicate new form of > false) > > // Define Predicate New relation > def getPredNewOpcode : InstrMapping { > let FilterClass = "PredNewRel"; > > let RowFields = ["BaseOpcode"]; > > // ColFields is a list of flags/attributes of the instructions. > let ColFields = ["DotNewType", "PredSense"]; > > // Here 'DotNewType' of th...

...ed under lib/Target/X86. A new pass is to be added at the pre-emit stage. It might be better to have TableGen generate the mapping table for you instead of manually making a table yourself. TableGen has a feature that is specifically designed to make mapping tables like this. For examples, grep for InstrMapping in: lib/Target/Hexagon/Hexagon.td lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/Mips32r6InstrFormats.td lib/Target/PowerPC/PPC.td lib/Target/AMDGPU/SIInstrInfo.td lib/Target/AMDGPU/R600Instructions.td lib/Target/SystemZ/SystemZInstrFormats.td lib/Ta...

...on rather than having to figure out the new opcode you need to > use. What AMDGPU does is define various RegisterOperands with custom types > that are allowed by the verifier to contain immediates. The same principle > should also work for mem operands. You could also try to define an > InstrMapping to get the other versions of the opcode. > > -Matt > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170412/0766b7d4/attachment.html>

Hi Jakob, Here is the first draft of the patch to add TableGen backend support for the instruction mapping tables. Please take a look and let me know your suggestions. As of now, I create one mapping table per relation which results into a long .inc file. So, I'm planning to combine everything into a single table and will include APIs (one per relation) to query from this table. Thanks,