Displaying 8 results from an estimated 8 matches for "instrformats".
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instrformat
2008 Oct 28
1
[LLVMdev] Accessing InstrFormat.td fields
When I setup my InstrFormat fields, I added some custom fields specific
for my backend. How do I access these from inside LLVM?
For example:
class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMD";
dag OutOperandList = outs;
dag InOperandList = ins;
let Pattern = pattern;
let
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
>
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> HexagonInstrInfo.td file and use TableGen to generate a table with
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...// the record values the current class to inherit has
for (unsigned i = 0, e = NewRecDefs.size(); i != e; ++i) {
Record *CurRec = NewRecDefs[i];
**** proposed changes -begin *****
if (SubClass.Rec->isSubClassOf("Relations")) {
std::vector<Init*> InstrFormats(SubClass.Rec->getValues().size());
1) Traverse thru all the records to see if CurRec's InstrFormat is
same as the ParentFormat for any of the
records and they both share same ancestors. If so, insert that
record at the appropriate place in the
vector using the...
2013 Feb 24
4
[LLVMdev] backend documentation
Hello everyone!
Is there any documentation about LLVM backend implementation, except
"Writing an LLVM backend"? I'm trying to write InstrFormats.td and
InstrInfo.td for my backend now. After reading "Writing an LLVM backend"
and "Creating an LLVM Backend for the Cpu0 Architecture", many black holes
have remained. These tutorials describe it on concrete examples, but
general approach is missed. For example, how to impleme...
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
Hi,
I'm looking for some suggestions on a problem related to the Hexagon
backend.
Hexagon architecture allows instructions in various formats. For example, we
have 3 variations of the add instruction as defined below:
ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 =
add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is
true ADDrr_np :
2015 Oct 19
2
Instructions with no operand
Hi all,
I am trying to implement an instruction with no operand for example "clr"
in TableGen.
-----------------------------------------
e.g.
*InstrInfo.td:*
class TestInst<string opc, string asmstr, dag oops, dag iops,
list<dag> pattern> : Instruction { ... }
def int_no_operand : Intrinsic<[]>;
class ALU<string opc> : TestInst<opc,
2013 Feb 24
0
[LLVMdev] backend documentation
...;
> Date: Sat, Feb 23, 2013 at 8:47 PM
> Subject: [LLVMdev] backend documentation
> To: llvmdev at cs.uiuc.edu
>
>
> Hello everyone!
>
> Is there any documentation about LLVM backend implementation, except
> "Writing an LLVM backend"? I'm trying to write InstrFormats.td and
> InstrInfo.td for my backend now. After reading "Writing an LLVM
> backend" and "Creating an LLVM Backend for the Cpu0 Architecture",
> many black holes have remained. These tutorials describe it on
> concrete examples, but general approach is missed. For exa...
2013 Feb 24
0
[LLVMdev] backend documentation
...back and read
and re-read them many times in order to grock the whole thing.
Reed
On 02/23/2013 05:47 PM, Vadim Khoptynets wrote:
> Hello everyone!
>
> Is there any documentation about LLVM backend implementation, except
> "Writing an LLVM backend"? I'm trying to write InstrFormats.td and
> InstrInfo.td for my backend now. After reading "Writing an LLVM backend"
> and "Creating an LLVM Backend for the Cpu0 Architecture", many black
> holes have remained. These tutorials describe it on concrete examples,
> but general approach is missed. For exa...