Displaying 2 results from an estimated 2 matches for "instmyarch".
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...CisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//define the instruction
def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
"cmp $src1 $src2;",
[(MYcmpicc IntRegs:$src1, IntRegs:$src2)]>;
Thanks for having a look on this.
If the problem lies not in my .td files, where else do you think I could dig for the ca...
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp,
> [SDNPOutFlag]>;
>
>
> //define the instruction
> def MYcmp : InstMYArch<(outs), (ins IntRegs:$src1, IntRegs:$src2),
> "cmp $src1 $src2;",
> [(MYcmpicc IntRegs:$src1, IntRegs:$src2)]>;
>
>
> Thanks for having a look on this.
> If the problem lies not in my .td files, where else do you th...