Displaying 4 results from an estimated 4 matches for "instmc".
2012 Aug 06
2
[LLVMdev] Tablegen foreach
That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
multiclass instmcRegImm<...> {
def rr: inst<...>;
def ri: inst<...>;
def ir: inst<...>;
def ii: inst<...>;
}
multiclass instmc<...> {
defm i8 : instmcRegImm<...>;
^-- repeat for 15 more register classes.
}
defm INST : instMC<..>;
Then I need to repeat this for SDNodes...
2012 Aug 06
0
[LLVMdev] Tablegen foreach
...an Silva
On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this:
>
> multiclass instmcRegImm<...> {
> def rr: inst<...>;
> def ri: inst<...>;
> def ir: inst<...>;
> def ii: inst<...>;
> }
> multiclass instmc<...> {
> defm i8 : instmcRegImm<...>;
> ^-- repeat for 15 more register classes.
> }
> defm INST : instMC&...
2012 Aug 06
0
[LLVMdev] Tablegen foreach
I think a multiclass may be a better fit for what you are trying to
do. In fact, this is the canonical example for multiclasses:
<http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>.
--Sean Silva
On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> I’m trying to find examples of the foreach pattern being used in
2012 Aug 06
2
[LLVMdev] Tablegen foreach
I'm trying to find examples of the foreach pattern being used in tablegen files.
The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal.
So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations.
Instead of writing all the combinations out, I'd like to use