Displaying 3 results from an estimated 3 matches for "instld".
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insted
2016 Jan 06
2
DFAPacketizer, Scheduling and LoadLatency
...uded
that the connection between LoadLatency and a given instruction is through
mayLoad variable. In other words an instruction will set its latency value
to LoadLatency if mayLoad is set to 1. However this doesn't seem to be
happening in my case.
Here is my load instruction definition:
class InstLD<bits<4> op, dag outs, dag ins, string asmstr, list<dag>
pattern>
: InstEscala<outs, ins, asmstr, pattern> {
let optype = 0b10;
let opcode = op;
}
class LOAD<bits<4> subop, string asmstring, list<dag> pattern>
: InstLD<subop, (outs GPR:$rD), (ins...
2015 Nov 17
2
DFAPacketizer, Scheduling and LoadLatency
> In particular, the LoadLatency is used in defaultDefLatency:
>
> /// Return the default expected latency for a def based on it's opcode.
> unsigned TargetInstrInfo::defaultDefLatency(
> const MCSchedModel &SchedModel, const MachineInstr *DefMI) const {
> if (DefMI->isTransient())
> return 0;
> if (DefMI->mayLoad())
> return
2016 Mar 30
3
infer correct types from the pattern
i'm getting a
Could not infer all types in pattern!
error in my backend. it is happening on the following instruction:
VGETITEM: (set GPR:{i32:f32}:$rD, (extractelt:{i32:f32}
VR:{v4i32:v4f32}:$rA, GPR:i32:$rB)).
how do i make it use appropriate types? in other words if it is f32 then
use v4v32 and if it is i32 then use v4f32. i'm not sure even where to start?
any help is appreciated.