Displaying 3 results from an estimated 3 matches for "instescala".
2016 Jan 06
2
Pattern doesn't match error
I made a small change to my target and them tried to recompile it. The
following error showed up:
error: Pattern doesn't match mayLoad = 0
A little bit of searched revealed that it came from here:
https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/CodeGenDAGPatterns.cpp#L2861
Unfortunately I can't understand what it means. Can someone help me out?
--
Rail Shafigulin
2016 Jan 06
2
DFAPacketizer, Scheduling and LoadLatency
...le. In other words an instruction will set its latency value
to LoadLatency if mayLoad is set to 1. However this doesn't seem to be
happening in my case.
Here is my load instruction definition:
class InstLD<bits<4> op, dag outs, dag ins, string asmstr, list<dag>
pattern>
: InstEscala<outs, ins, asmstr, pattern> {
let optype = 0b10;
let opcode = op;
}
class LOAD<bits<4> subop, string asmstring, list<dag> pattern>
: InstLD<subop, (outs GPR:$rD), (ins MEMri:$src),
!strconcat(asmstring, "\t$rD, $src"), pattern> {
bits<5...
2015 Nov 17
2
DFAPacketizer, Scheduling and LoadLatency
> In particular, the LoadLatency is used in defaultDefLatency:
>
> /// Return the default expected latency for a def based on it's opcode.
> unsigned TargetInstrInfo::defaultDefLatency(
> const MCSchedModel &SchedModel, const MachineInstr *DefMI) const {
> if (DefMI->isTransient())
> return 0;
> if (DefMI->mayLoad())
> return