Displaying 2 results from an estimated 2 matches for "instertelement".
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insertelement
2007 Sep 27
3
[LLVMdev] Vector swizzling and write masks code generation
...ucts (as GLSL, HLSL and
few others are) I'd like to make sure that the code generator is actually
capable of generating instructions with exactly those semantics.
Right now vector operations utilizing swizzling and write masks in LLVM IR
have to expressed with series of load/extractelement/instertelement/store
constructs. As in
vec2 = vec4.xy
would end up being:
%tmp = load <4 x float>* @vec4
%tmp1 = extractelement <4 x float> %tmp, i32 0
%tmp2 = insertelement <2 x float> undef, float %tmp1, i32 0
%tmp3 = extractelement <4 x float> %tmp, i32 1
%tmp4 = insertelement <...
2007 Sep 27
0
[LLVMdev] Vector swizzling and write masks code generation
...rator is actually
> capable of generating instructions with exactly those semantics.
Ok. Are you planning to use the LLVM code generator, or roll your own?
> Right now vector operations utilizing swizzling and write masks in LLVM IR
> have to expressed with series of load/extractelement/instertelement/store
> constructs. As in
>
> vec2 = vec4.xy
>
> would end up being:
> %tmp = load <4 x float>* @vec4
> %tmp1 = extractelement <4 x float> %tmp, i32 0
> %tmp2 = insertelement <2 x float> undef, float %tmp1, i32 0
> %tmp3 = extractelement <4 x float>...