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.../11/2012 12:48 PM, Andrew Trick wrote: > Ignoring compile time for a moment, I think an advantage of a DFA is modeling a situation where the hardware can assign resources to best fit the entire group rather then one instruction at a time. For example, if InstA requires either Unit0 or Unit1, and InstB requires Unit0, is {InstA, InstB} a valid group? Depending on your cpu, a DFA could either recognize that it's valid, or give you a chance to reorder the instructions within a group once they've been selected. > I would recommend the DFA mechanism as well from what you've described....

...k either if you feel compelled to do that. Ignoring compile time for a moment, I think an advantage of a DFA is modeling a situation where the hardware can assign resources to best fit the entire group rather then one instruction at a time. For example, if InstA requires either Unit0 or Unit1, and InstB requires Unit0, is {InstA, InstB} a valid group? Depending on your cpu, a DFA could either recognize that it's valid, or give you a chance to reorder the instructions within a group once they've been selected. Ideally, you can express your constraints using InstrStage itinerary entries. If...

I'm considering writing more-detailed itineraries for some PowerPC CPUs that use the 'traditional' instruction grouping scheme. In essence, this means that multiple instructions will stall in some pipeline stage until a complete group is formed, then all will continue. I expect to provide CPU-specific code to help determine when the currently-waiting instructions would form a group.

...Is that correct? > > Ignoring compile time for a moment, I think an advantage of a DFA is > modeling a situation where the hardware can assign resources to best > fit the entire group rather then one instruction at a time. For > example, if InstA requires either Unit0 or Unit1, and InstB requires > Unit0, is {InstA, InstB} a valid group? Depending on your cpu, a DFA > could either recognize that it's valid, or give you a chance to > reorder the instructions within a group once they've been selected. In the PowerPC grouping scheme, resources are assigned on a group...

On Thu, Mar 29, 2012 at 03:51:10PM -0700, Andrew Trick wrote: > > On Mar 29, 2012, at 1:18 PM, Tom Stellard <thomas.stellard at amd.com> wrote: > > > On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > >> Tom, > >> > >> I do not have your call stack, but packetizer calls > >> ScheduleDAGInstrs::buildSchedGraph to create