Displaying 5 results from an estimated 5 matches for "instarm".
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2006 May 01
2
[LLVMdev] problems with tablegen and namespaces
I am trying to write a skeleton of an ARM back end. I have declared
the following class
class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Namespace = "ARM";
dag OperandList = ops;
let AsmString = asmstr;
let Pattern = pattern;
}
and defined three instructions (ldr, str, and mov).
The problem is that, in the generated code, the namespace...
2013 Sep 01
0
[LLVMdev] llvm-tblgen for ARMInstrFormats.td with !if(a,b,c)
Hi,
I wonder whether I can conditionally set AsmString in class sI. For
instance, I would like to know whether it is possible to establish some int
or bit operator to check whether bits<4> p is 14. What I would like to do
is to set AsmString as follows,
class sI<...> :InstARM<....> {
...
let AsmString = !if(some operator, !strconcat(ppc, "${s}", asm),
!strconcat(ppc, "${p}${s}", asm);
...
}
Thanks,
--
UGR
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2006 May 01
0
[LLVMdev] problems with tablegen and namespaces
On Mon, 1 May 2006, [UTF-8] Rafael Esp?ndola wrote:
> I am trying to write a skeleton of an ARM back end. I have declared
> the following class
>
> class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
> let Namespace = "ARM";
>
> dag OperandList = ops;
> let AsmString = asmstr;
> let Pattern = pattern;
> }
>
> and defined three instructions (ldr, str, and mov).
>
> The problem is that...
2015 Jul 10
0
[LLVMdev] TSFlags
On 7/10/2015 10:23 AM, Sky Flyer wrote:
> Many thanks for your prompt reply.
>
> I mean, imagine you have 3 bits for condition flags in your instruction
> (e.g. overflow, zero, carry set, ...) for conditional executions AND
> there is no direct access to the Status Register, is it even possible to
> implement such scenario?
>
There doesn't have to be any explicit status
2015 Jul 10
3
[LLVMdev] TSFlags
Many thanks for your prompt reply.
I mean, imagine you have 3 bits for condition flags in your instruction
(e.g. overflow, zero, carry set, ...) for conditional executions AND there
is no direct access to the Status Register, is it even possible to
implement such scenario?
On Fri, Jul 10, 2015 at 4:54 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 7/10/2015 9:32