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2011 Nov 03
3
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...an example of something I have
tried. It fails to compile with tablegen, but I hope it can help
demonstrate what I am trying to do:
def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>;
def F32Op : Operand <f32> {
let MIOperandInfo = (ops GPR, f32imm);
}
def ADD : InstAMD <
(outs GPR:$dst),
(ins F32Op:$src0, F32Op:$src1),
"ADD $dst, $src0, $src1"),
[(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))]
>;
Is what I am trying to do possible with tablegen, and if so what is the
best way for me to do it?
Thanks...
2011 Nov 03
0
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...o compile with tablegen, but I hope it can help
> demonstrate what I am trying to do:
>
>
> def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>;
>
> def F32Op : Operand <f32> {
> let MIOperandInfo = (ops GPR, f32imm);
> }
>
> def ADD : InstAMD <
> (outs GPR:$dst),
> (ins F32Op:$src0, F32Op:$src1),
> "ADD $dst, $src0, $src1"),
> [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))]
> >;
>
> Is what I am trying to do possible with tablegen, and if so what is th...