search for: insl

...N__.21766+0x1c> > + 43b: 78 5f js 49c <__FUNCTION__.21679+0x1c> > 43d: 65 gs > 43e: 71 75 jno 4b5 <.str5+0x6> > 440: 61 popa > @@ -11707,25 +11707,25 @@ > 449: 6d insl (%dx),%es:(%edi) > 44a: 72 65 jb 4b1 <.str5+0x2> > 44c: 66 5f pop %di > - 44e: 70 00 jo 450 <__FUNCTION__.21323> > + 44e: 70 00 jo 450 <__FUNCTION__.21236> > > -00000450 <__FU...

...ion of 'outw_p' include/asm-generic/io.h:676:16: error: redefinition of 'outl_p' include/asm-generic/io.h:689:14: error: redefinition of 'insb' include/asm-generic/io.h:697:14: error: redefinition of 'insw' include/asm-generic/io.h:705:14: error: redefinition of 'insl' include/asm-generic/io.h:713:15: error: redefinition of 'outsb' include/asm-generic/io.h:722:15: error: redefinition of 'outsw' include/asm-generic/io.h:731:15: error: redefinition of 'outsl' Unverified Error/Warning (likely false positive, please contact us if interes...

The saga continues. I've been tracking the interface changes and merging them with the refactoring work I'm doing. I got as far as building stage3 of llvm-gcc but the object files from stage2 and stage3 differ: warning: ./cc1-checksum.o differs warning: ./cc1plus-checksum.o differs (Are the above two ok?) The list below is clearly bad. I think it's every object file in the

...: "+D" (__d), "+c"(__n) + : "d"(__p)); +} + +static __inline__ void insw(__u16 __p, void *__d, __u64 __n) +{ + asm volatile ("cld; rep; insw" + : "+D" (__d), "+c"(__n) + : "d"(__p)); +} + +static __inline__ void insl(__u16 __p, void *__d, __u64 __n) +{ + asm volatile ("cld; rep; insl" + : "+D" (__d), "+c"(__n) + : "d"(__p)); +} + +#endif /* _SYS_IO_H */ diff --git a/usr/klibc/SYSCALLS.def b/usr/klibc/SYSCALLS.def index 41cfa17..e62a9e8 100644 --- a/usr/klibc/SYS...

...d), "+c"(__n) + : "d"(__p)); +} + +static __inline__ void insw(unsigned short __p, void *__d, unsigned long __n) +{ + asm volatile ("cld; rep; insw" + : "+D" (__d), "+c"(__n) + : "d"(__p)); +} + +static __inline__ void insl(unsigned short __p, void *__d, unsigned long __n) +{ + asm volatile ("cld; rep; insl" + : "+D" (__d), "+c"(__n) + : "d"(__p)); +} + +#endif /* _SYS_IO_H */ diff --git a/usr/klibc/arch/x86_64/MCONFIG b/usr/klibc/arch/x86_64/MCONFIG new file mo...

...16 port, VMI_UINT32 count) +{ + vmi_wrap_call( + OUTSW, "rep; outsw", + VMI_NO_OUTPUT, + 3, XCONC("S"(addr), "c"(count), "d"(port)), + VMI_CLOBBER_EXTENDED(ZERO_RETURNS, "esi", "ecx", "memory")); +} + +static inline void vmi_insl(VMI_UINT32 *addr, const VMI_UINT16 port, VMI_UINT32 count) +{ + vmi_wrap_call( + INS, "rep; insl", + VMI_NO_OUTPUT, + 3, XCONC("D"(addr), "c"(count), "d"(port)), + VMI_CLOBBER_EXTENDED(ZERO_RETURNS, "edi", "ecx", "memory"));...

...16 port, VMI_UINT32 count) +{ + vmi_wrap_call( + OUTSW, "rep; outsw", + VMI_NO_OUTPUT, + 3, XCONC("S"(addr), "c"(count), "d"(port)), + VMI_CLOBBER_EXTENDED(ZERO_RETURNS, "esi", "ecx", "memory")); +} + +static inline void vmi_insl(VMI_UINT32 *addr, const VMI_UINT16 port, VMI_UINT32 count) +{ + vmi_wrap_call( + INS, "rep; insl", + VMI_NO_OUTPUT, + 3, XCONC("D"(addr), "c"(count), "d"(port)), + VMI_CLOBBER_EXTENDED(ZERO_RETURNS, "edi", "ecx", "memory"));...

..."+c" (__n) + : "d" (__p)); +} + +static __inline__ void insw(unsigned short __p, void *__d, unsigned long __n) +{ + asm volatile ("cld; rep; insw" + : "+D" (__d), "+c" (__n) + : "d" (__p)); +} + +static __inline__ void insl(unsigned short __p, void *__d, unsigned long __n) +{ + asm volatile ("cld; rep; insl" + : "+D" (__d), "+c" (__n) + : "d" (__p)); +} + +#endif /* _SYS_IO_H */ diff --git a/usr/include/arch/i386/sys/vm86.h b/usr/include/arch/i386/sys/vm86.h new...

...tatic void ioport_read16r(const void __iomem *addr, void *dst, unsigned long count) { insw(ADDR2PORT(addr), dst, count); } -static void ioport_read32r(void __iomem *addr, void *dst, unsigned long count) +static void ioport_read32r(const void __iomem *addr, void *dst, unsigned long count) { insl(ADDR2PORT(addr), dst, count); } @@ -150,37 +150,37 @@ static const struct iomap_ops ioport_ops = { /* Legacy I/O memory ops */ -static unsigned int iomem_read8(void __iomem *addr) +static unsigned int iomem_read8(const void __iomem *addr) { return readb(addr); } -static unsigned int iom...

...tatic void ioport_read16r(const void __iomem *addr, void *dst, unsigned long count) { insw(ADDR2PORT(addr), dst, count); } -static void ioport_read32r(void __iomem *addr, void *dst, unsigned long count) +static void ioport_read32r(const void __iomem *addr, void *dst, unsigned long count) { insl(ADDR2PORT(addr), dst, count); } @@ -150,37 +150,37 @@ static const struct iomap_ops ioport_ops = { /* Legacy I/O memory ops */ -static unsigned int iomem_read8(void __iomem *addr) +static unsigned int iomem_read8(const void __iomem *addr) { return readb(addr); } -static unsigned int iom...

...tatic void ioport_read16r(const void __iomem *addr, void *dst, unsigned long count) { insw(ADDR2PORT(addr), dst, count); } -static void ioport_read32r(void __iomem *addr, void *dst, unsigned long count) +static void ioport_read32r(const void __iomem *addr, void *dst, unsigned long count) { insl(ADDR2PORT(addr), dst, count); } @@ -150,37 +150,37 @@ static const struct iomap_ops ioport_ops = { /* Legacy I/O memory ops */ -static unsigned int iomem_read8(void __iomem *addr) +static unsigned int iomem_read8(const void __iomem *addr) { return readb(addr); } -static unsigned int iom...

Hi, Multiple architectures are affected in the first patch and all further patches depend on the first. Maybe this could go in through Andrew Morton's tree? Changes since v2 ================ 1. Drop all non-essential patches (cleanups), 2. Update also drivers/sh/clk/cpg.c . Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add Geert's review, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add acks and reviews, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add acks and reviews, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

Hi, Changes since v1 ================ https://lore.kernel.org/lkml/1578415992-24054-1-git-send-email-krzk at kernel.org/ 1. Constify also ioreadX_rep() and mmio_insX(), 2. Squash lib+alpha+powerpc+parisc+sh into one patch for bisectability, 3. Add acks and reviews, 4. Re-order patches so all optional driver changes are at the end. Description =========== The ioread8/16/32() and others have

I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: