search for: insertnoop

...#39;ve built a pass to split critical edges of machine functions, and I have >> to insert new basic blocks. Some of them will have MBB->begin() == >> MBB->end(). > > Ah, machine basic blocks are different. They *are* allowed to be empty. > I would like to build an "insertNoOp" and add it to MRegisterInfo. I would have one for each target. For the x86 I am moving the stack pointer to itself. Is there a better "no-op"? A better one would be one that does not use any register, so it will add absolutely no burden on the register allocator. Fernando

For adding the nop: TII->insertNoop(*BB, BB->end()); 2007/8/9, Chris Lattner <sabre at nondot.org>: > > On Thu, 9 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > I too believe it should not be complicated. > > But I was not being able to do it. > > Finally, after some thinking (and tinkering), this...

Dan: CellSPU could clearly benefit from the post-RA scheduler. In fact, we were thinking about writing a machine pass of our own. One thing that does "disturb" me is that both HazardRecognizer and post-RA sched assume there's only one kind of NOP. For Cell, there are two, depending upon the pipeline being filled. Pipe 0 takes "ENOP" whereas Pipe 1 take

>> I am in need of a no-op instruction: an instruction that does not do >> anything, and has no operands. Does LLVM predefine such an instruction? I >> want to transform the program so that there is no empty basic block. > > You can never have an empty basic block. All BBs must have a TerminatorInst. > I've built a pass to split critical edges of machine

On Fri, 13 Jul 2007, Fernando Magno Quintao Pereira wrote: >> You can never have an empty basic block. All BBs must have a TerminatorInst. >> > > I've built a pass to split critical edges of machine functions, and I have > to insert new basic blocks. Some of them will have MBB->begin() == > MBB->end(). Ah, machine basic blocks are different. They *are* allowed

...functions, >>> and I have >>> to insert new basic blocks. Some of them will have MBB->begin() == >>> MBB->end(). >> >> Ah, machine basic blocks are different. They *are* allowed to be >> empty. >> > > I would like to build an "insertNoOp" and add it to MRegisterInfo. > I would > have one for each target. For the x86 I am moving the stack pointer to > itself. Is there a better "no-op"? A better one would be one that > does not > use any register, so it will add absolutely no burden on the register &...

On Thu, 9 Aug 2007, [ISO-8859-1] Em�lio Wuerges wrote: > I too believe it should not be complicated. > But I was not being able to do it. > Finally, after some thinking (and tinkering), this worked like a charm: > > MachineInstr* mi = BB->remove(BB->begin()); > BB->push_back(mi); > > But, is there a better way to do it? This is a good way to do a single

...And this worked. Flawlessly. Without the error. But this is useless ^_^. Can someone help me to understand this behavior? PS, beware code above, I just tested it, not proven it correct, hehe. 2007/8/9, Emílio Wuerges <wuerges at gmail.com>: > > For adding the nop: > > TII->insertNoop(*BB, BB->end()); > > > 2007/8/9, Chris Lattner <sabre at nondot.org>: > > > > On Thu, 9 Aug 2007, [ISO-8859-1] Emílio Wuerges wrote: > > > I too believe it should not be complicated. > > > But I was not being able to do it. > > > Finally, aft...

Hello. I am new to the schedulers implemented in the back end of LLVM. I am trying to handle data hazards in my simple processor, with instructions that execute in 1 cycle. I have tried the standard post-RA scheduler, implemented in lib/CodeGen/PostRASchedulerList.cpp, (with a ScoreboardHazardRecognizer), but I have some issues with some consecutive instructions that are

...and otherwise, I give: return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); - I implemented in [Target]InstrInfo.cpp 2 more methods: - CreateTargetPostRAHazardRecognizer() to register the [Target]DispatchGroupSBHazardRecognizer() - insertNoop() which returns the target's NOP - note that my vector (and scalar) instructions are inspired from the Mips back end, which has MSAInst (and MipsInst) with NoItinerary InstrItinClass. Currently I am not using a [Target]Schedule.td specifying functional units, processor and instruction...

Hi Tanya and everybody, Ty for your support. I too believe it should not be complicated. But I was not being able to do it. For instance, I tried to run this code below: BB->push_back(&(BB->front())); BB->pop_front(); But it did not work (kinda obvious why). Nor this: BB->push_back(BB->begin()); BB->pop_front(); But also did not work. It seams the same

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure:

...int)in libLLVMEBCCodeGen.a(EBCRegisterInfo.cpp.o) "llvm::TargetLoweringObjectFile::getSectionForConstant(llvm::SectionKind) const", referenced from: vtable for llvm::TargetLoweringObjectFileCOFFin libLLVMCodeGen.a(TargetLoweringObjectFileImpl.cpp.o) "llvm::TargetInstrInfo::insertNoop(llvm::MachineBasicBlock&, llvm::ilist_iterator<llvm::MachineInstr>) const", referenced from: vtable for llvm::EBCInstrInfoin libLLVMEBCCodeGen.a(EBCTargetMachine.cpp.o) vtable for llvm::TargetInstrInfoImplin libLLVMCodeGen.a(TargetInstrInfoImpl.cpp.o) vtable for llv...