search for: insertfencesforatom

> Longer term, I hope to improve the fence elimination of the ARM backend with > a kind of PRE algorithm. Both of these improvements to the ARM backend > should be fairly straightforward to port to the POWER architecture later, > and I hope to also do that. > > Any reason these couldn't be done at the IR level? I definitely agree here. At the time, it was a plausible idea

...ake time to do so, hence my questions here). It's completely unacceptable to give LLVM's "fence whatever" a target-specific meaning in my opinion, even briefly. > Another thing I would have to move to this IR pass is the insertion of > fences around atomic stores/loads when insertFencesForAtomic==true. It is > currently happening in SelectionDAGBuilder, which makes it impossible to do > fence elimination at the IR level. I'm a little worried about this being just one monster "do stuff with atomics" pass, especially if it ends up one-per-target, but even if the bulk c...

...d + dependant useless branch + isb is also valid (see http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html for example) and may be faster. Even better: if there is already a dependant branch (such as the loop for the lowering of CAS), it is just a cheap isb. The main step will be switching off the InsertFencesForAtomic flag, and do the lowering of atomics in the backend, because once an acquire load has been transformed in an acquire fence, too much information has been lost to apply this mapping. Longer term, I hope to improve the fence elimination of the ARM backend with a kind of PRE algorithm. Both of thes...