search for: insertelt

Hello, I've added a little combining operation in DAGCombiner to fold a chain of insertelt nodes if that chain is proved to fully overwrite the very first source vector. In which case, I supposed a build_vector is better. It seems to be safe but I don't know if it is correctly implemented or if it is already done somewhere else. Please find attached the patch. Regards, Ivan -----...

On Feb 17, 2012, at 12:50 AM, Ivan Llopard wrote: > Hello, > > I've added a little combining operation in DAGCombiner to fold a chain of insertelt nodes if that chain is proved to fully overwrite the very first source vector. In which case, I supposed a build_vector is better. It seems to be safe but I don't know if it is correctly implemented or if it is already done somewhere else. Please find attached the patch. Hi Ivan, This needs a...

...essor that has complex type registers. >> It has two functional units to perform complex multiplications. >> From clang, I emulate a complex multiplication using vectors and, at >> the IR, I got this tblgen-friendly pattern (real component) : >> >> (set RARegs:$dst, (insertelt RARegs:$src, >> (i16 (trunc (add >> (ncmul >> (sext (i16 (extractelt RARegs:$a, imm))), >> (sext (i16 (extractelt RARegs:$b, imm))) >> ), >> (ncmul >> (sext (i16 (extract...

...lex type registers. >>> It has two functional units to perform complex multiplications. >>>  From clang, I emulate a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>>           (i16 (trunc (add >>>            (ncmul >>>             (sext (i16 (extractelt RARegs:$a, imm))), >>>             (sext (i16 (extractelt RARegs:$b, imm))) >>>             ), >>>            (ncmul >>>          ...

...gt;>>> It has two functional units to perform complex multiplications. >>>> From clang, I emulate a complex multiplication using vectors and, at >>>> the IR, I got this tblgen-friendly pattern (real component) : >>>> >>>> (set RARegs:$dst, (insertelt RARegs:$src, >>>> (i16 (trunc (add >>>> (ncmul >>>> (sext (i16 (extractelt RARegs:$a, imm))), >>>> (sext (i16 (extractelt RARegs:$b, imm))) >>>> ), >>>>...

Hi all, I am writing a back-end for a processor that has complex type registers. It has two functional units to perform complex multiplications. From clang, I emulate a complex multiplication using vectors and, at the IR, I got this tblgen-friendly pattern (real component) : (set RARegs:$dst, (insertelt RARegs:$src, (i16 (trunc (add (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARegs:$b, imm))) ), (ncmul (sext (i16 (extractelt RARegs:$a, imm))), (sext (i16 (extractelt RARe...

...a back-end for a processor that has complex type registers. > It has two functional units to perform complex multiplications. >  From clang, I emulate a complex multiplication using vectors and, at > the IR, I got this tblgen-friendly pattern (real component) : > > (set RARegs:$dst, (insertelt RARegs:$src, >           (i16 (trunc (add >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >             (sext (i16 (extractelt RARegs:$b, imm))) >             ), >            (ncmul >             (sext (i16 (extractelt RARegs:$a, imm))), >        ...

...ex type registers. >>> It has two functional units to perform complex multiplications. >>> From clang, I emulate a complex multiplication using vectors and, at >>> the IR, I got this tblgen-friendly pattern (real component) : >>> >>> (set RARegs:$dst, (insertelt RARegs:$src, >>> (i16 (trunc (add >>> (ncmul >>> (sext (i16 (extractelt RARegs:$a, imm))), >>> (sext (i16 (extractelt RARegs:$b, imm))) >>> ), >>> (ncmul >>>...

...; it's used inside > the custom lowering for INSERT_VECTOR_ELT and VECTOR_SHUFFLE. Yes, that's how I found out about it. :) Why not just use ISD::INSERT_VECTOR_ELT? And what's the difference between vector_extract and extractelt in TargetSelectionDAG.td? Ditto vector_insert vs. insertelt. -Dave

...o i16 br i1 %cmp, label %for.body, label %for.end for.end: ; preds = %for.body store i32 50, i32* @i, align 4 store <2 x i16> %6, <2 x i16>* @c, align 4 ret void } The store to "c" is efficiently moved out of the loop but insertelt and extractelt are not. Because we are always accessing the second element of vector c, is it not more efficient to move extractelt to the loop entry and insertelt to the end ? Ivan

On Wed, Dec 2, 2009 at 3:08 PM, David Greene <dag at cray.com> wrote: > On Wednesday 02 December 2009 16:51, Eli Friedman wrote: >> On Wed, Dec 2, 2009 at 2:44 PM, David Greene <dag at cray.com> wrote: >> > I'm working on some of the AVX insert/extract instructions.  They're >> > stupid.  They do not operate on ymm registers, meaning we have to

On Wednesday 02 December 2009 16:51, Eli Friedman wrote: > On Wed, Dec 2, 2009 at 2:44 PM, David Greene <dag at cray.com> wrote: > > I'm working on some of the AVX insert/extract instructions.  They're > > stupid.  They do not operate on ymm registers, meaning we have to > > use VINSERTF128/VEXTRACTF128 and then do the real operation. > > > > Anyway,

Hello, is there a good way to determine that the instruction is a vector instruction? Or the only way like it's size is multiple of the operands size? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170829/bbe6213b/attachment.html>