search for: insertbranch

According to the docs, InsertBranch should only be called if AnalyzeBranch returns success. But in targets (like ARM or Sparc) that don't implement them, the following test fails: ----------------------------------- void %__gcov_init() { entry: switch uint 0, label %cond_true.i [ uint 0, label %UnifiedRe...

...t directly before LBB0_34 though. It would be interesting to see the blocks before and after the "Basic block placement" pass. Running llc with -print-after-all and/or -debug might well shed some light on what's happening. Other possible bugs are in implementations of AnalyzeBranch, InsertBranch or RemoveBranch. They're target callbacks LLVM uses to do its more invasive block movement. The place to start debugging is lib/CodeGen/MachineBlockPlacement.cpp. Something in there is probably getting confused. Cheers. Tim.

Hi, guys, I compiled a subroutine with -O2, and llvm backend produced codes like: ################################################################## LBB0_32: ... R31 = -1 R20 = R31 * R20; .... bnz R2, LBB0_34 LBB0_31: ... b LBB0_34 LBB0_33: # weird basic block? R20 = R5 LBB0_34: ....

Fernando, The code there should be more or less functional, though it's not currently used by anything. Eventually it should probably be moved to a method on MachineBasicBlock. The API breakage you're seeing is because some methods moved around. Feel free to fix it. :-) --Owen On Jan 26, 2008, at 6:31 PM, Fernando Magno Quintao Pereira wrote: > > Hi LLVMers, > >

Hi LLVMers, what is the status of breaking critical edges in machine functions? I just compiled the top of the LLVM tree, and I found llvm/CodeGen/BreakCriticalMachineEdge.h. But this file seems not to be up-to-date with the other classes in the top of the tree. For instance, it calls isTerminatorInstr on llvm::TargetInstrInfo, but this method is no longer there. If I want to break

I want to be able to do two things with LLVM (both just before code emission): 1. Insert a MachineBasicBlock just before a MachineBasicBlock. There is a function called AddPredecessor(). However, the comment says that it does not update the actual CFG. I want to redirect all CFG edges that are incoming to this MachineBasicBlock to the new one I create, and add just one outgoing edge (no branch)

Is LiveVariables updated correctly when TII->RemoveBranch and TII->InsertBranch are called in the following piece of code? - MachineBasicBlock::updateTerminator() line 307 of MachineBasicBlock.cpp: if (FBB) { // The block has a non-fallthrough conditional branch. If one of its // successors is its layout successor, rewrite it to a fallthrough // conditiona...

...d well during the branch transformations, and more specifically when new instructions are added to compute complementary predicates in physical registers that were not at all used or defined in the function at hand before, and when these registers are then used. But it is strange that in a sequence InsertBranch - RemoveBranch - InsertBranch - RemoveBranch all operating on an identical instruction, the first removal is successful, while the second asserts ... following the commit of r161643 Can you shed some light on this, on where to look further for example? Thanks a lot, Bjorn

...instruction like this <pre> bne %r1, %r2, .label </pre> </BR> I am referring to sparc code for this implementation (llvm-3.1).</BR></BR> 1. Should I change the SPBranch and BCOND structs in .td file.</BR> 2. Should I change BuildMI constructs in SparcInstrInfo::InsertBranch() function in SparcInstrInfo.cpp</BR> Please help me. I am referring LLVM 3.1.</BR> Vikram -- View this message in context: http://llvm.1065342.n5.nabble.com/subcc-problem-wrt-sparc-tp53138.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

...These operands can be used to create new + /// branches. + /// 6. If the block ends with a conditional return followed by an + /// unconditional branch, the 'false' destination is FBB, while TBB is + /// null. Cond is non-empty as above. /// /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160531/b7086d8b/attachment.html> -------------- next part -------------- A non...

Hi All, For various obscure reasons I'd like to detect the condition when X86 CALL instruction immediately precedes a function epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin()

...ruction BZND (there are also other related instructions). I started this process by converting the Hexagon Hardware-Loops pass to work with analogous PPC instructions. This worked fairly well, but left a bunch of unneeded unconditional branches. To fix this, I added support into AnalyzeBranch (and InsertBranch and RemoveBranch). Unfortunately, this really broke things, the branch instructions (which both used and defined the count register) were moved around in invalid ways causing both compile-time (live-out assertions) and run-time failures. Instead of trying to track down these problems, I thought it...