search for: insert_subvector

On 2017-01-20 14:31, Hal Finkel wrote: > > On 01/20/2017 06:11 AM, Jonas Paulsson via llvm-dev wrote: >> Hi, >> >> I wonder why getScalarizationOverhead() does not take into account >> the number of operands of the instruction? This should influence the >> number of extracts needed, so instead of >> >> Scalarization cost = NumEls * (insert +

...of “cannot select" in the LLVM test suite with -march=core-avx-i. E.g., SingleSource/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 -march=core-avx-i with: fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = bitcast 0x7f91b99b0e10 [ORD=3] [ID=27] 0x7f91b99b0e10: v4i64 = insert_subvector 0x7f91b99a7210, 0x7f91b99a6d68, 0x7f91b99ace70 [ORD=2] [ID=25] 0x7f91b99a7210: v4i64 = undef [ID=15] 0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] [ID=23] 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738 [ORD=2] [ID=20] 0x7f91b99acc60: i64,ch =...

...t;> -march=core-avx-i. >> E.g., SingleSource/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 >> -march=core-avx-i with: >> fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = >> bitcast 0x7f91b99b0e10 [ORD=3] [ID=27] >> 0x7f91b99b0e10: v4i64 = insert_subvector 0x7f91b99a7210, >> 0x7f91b99a6d68, 0x7f91b99ace70 [ORD=2] [ID=25] >> 0x7f91b99a7210: v4i64 = undef [ID=15] >> 0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] >> [ID=23] >> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738 &gt...

...the LLVM test suite with -march=core-avx-i. >> E.g., SingleSource/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 -march=core-avx-i with: >> fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = bitcast 0x7f91b99b0e10 [ORD=3] [ID=27] >> 0x7f91b99b0e10: v4i64 = insert_subvector 0x7f91b99a7210, 0x7f91b99a6d68, 0x7f91b99ace70 [ORD=2] [ID=25] >> 0x7f91b99a7210: v4i64 = undef [ID=15] >> 0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] [ID=23] >> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60, 0x7f91b99ac738 [ORD=2] [ID=20] >&...

...t gives information about the min/max vector-width. As an example of how this was implemented, see e.g. https://reviews.llvm.org/D85117, where the lowering code generates a predicate for the specified VL and passes it to the instruction. * We extended the meaning of ISD::EXTRACT_SUBVECTOR and ISD::INSERT_SUBVECTOR in the context of scalable vectors, so that it is possible to insert/extract a fixed-width vector into or from a scalable vector. (https://reviews.llvm.org/D79806) * We added an intrinsic for vscale and corresponding ISD::VSCALE (https://reviews.llvm.org/D68203) What’s next? ============ The ne...

...vx-i. >>> E.g., SingleSource/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 >>> -march=core-avx-i with: >>> fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = >>> bitcast 0x7f91b99b0e10 [ORD=3] [ID=27] >>> 0x7f91b99b0e10: v4i64 = insert_subvector 0x7f91b99a7210, >>> 0x7f91b99a6d68, 0x7f91b99ace70 [ORD=2] [ID=25] >>> 0x7f91b99a7210: v4i64 = undef [ID=15] >>> 0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] >>> [ID=23] >>> 0x7f91b99ab840: i64 = AssertZext 0x7f91b99acc60...

On Fri, Sep 5, 2014 at 9:32 AM, Robert Lougher <rob.lougher at gmail.com> wrote: > Unfortunately, another team, while doing internal testing has seen the > new path generating illegal insertps masks. A sample here: > > vinsertps $256, %xmm0, %xmm13, %xmm4 # xmm4 = xmm0[0],xmm13[1,2,3] > vinsertps $256, %xmm1, %xmm0, %xmm6 # xmm6 = xmm1[0],xmm0[1,2,3] >

...be lowered into the vector register file. I have this design working for the case where the stack object's lifetime resides entirely within a single basic block: I start with an undef node to represent the set of registers to which the buffer is allocated, and replace stores to the buffer with insert_subvector's and replace loads with extract_subvector's. I'm now looking at generalizing the design for the case where the stack object's lifetime spans across 2 or more basic blocks and am hoping someone from the community will be able to offer a little insight so that if there are major iss...

...resulting in the extraction of the top half of the input vector. This maintains the intension of the original code for both scalable and non-scalable vectors. For common code that truly requires an absolute index we recommend a new distinct ISD node to better differentiate such patterns. ## *ISD::INSERT_SUBVECTOR* {#isdinsertsubvector} `INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX)` We have made the equivalent change to this node's index parameter to match the behaviour of [ISD::EXTRACT_SUBVECTOR](#ISD::EXTRACT_SUBVECTOR). ## *ISD::PROPAGATE\_FIRST\_ZERO* {#isdpropagatefirstzero} `PROPAGATE_FIRST_ZERO(VEC...

...Source/UnitTests/Vector/SSE/sse.isamax.c is failing at O3 >>>>> -march=core-avx-i with: >>>>> fatal error: error in backend: Cannot select: 0x7f91b99a6420: v4i32 = >>>>> bitcast 0x7f91b99b0e10 [ORD=3] [ID=27] >>>>> 0x7f91b99b0e10: v4i64 = insert_subvector 0x7f91b99a7210, >>>>> 0x7f91b99a6d68, 0x7f91b99ace70 [ORD=2] [ID=25] >>>>> 0x7f91b99a7210: v4i64 = undef [ID=15] >>>>> 0x7f91b99a6d68: v2i64 = scalar_to_vector 0x7f91b99ab840 [ORD=2] >>>>> [ID=23] >>>>> 0x7f91b99a...

In the spirit of the (long-term) intent to migrate away from the SelectionDAG framework, it is desirable to implement legalization passes as discrete passes. Attached is a patch which implements the beginning of a new type legalization pass, to help motivate discussion. Is LLVM IR the right level for this? The main alternative approach that's been discussed is to do FastISel to a