Displaying 3 results from an estimated 3 matches for "inrement".
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increment
2011 Jan 28
3
[LLVMdev] Post-inc combining
...ase address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this
is exactly what I would like to handle: a simple loop with an address that is inremented in each iteration.
I am considering using a target intrinsic for this purpose, as the SCEV interface is available on the LLVM I/R. In this way, I could get a DAG with a post-inc-load node instead of the load and add nodes.
Is this a work in progress? Please explain why these constraints are put...
2011 Jan 28
0
[LLVMdev] Post-inc combining
...ddress inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this
> is exactly what I would like to handle: a simple loop with an address that is inremented in each iteration.
>
> I am considering using a target intrinsic for this purpose, as the SCEV interface is available on the LLVM I/R. In this way, I could get a DAG with a post-inc-load node instead of the load and add nodes.
>
> Is this a work in progress? Please explain why these...
2011 Feb 07
1
[LLVMdev] Post-inc combining
...ase address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this
is exactly what I would like to handle: a simple loop with an address that is inremented in each iteration.
I am considering using a target intrinsic for this purpose, as the SCEV interface is available on the LLVM I/R. In this way, I could get a DAG with a post-inc-load node instead of the load and add nodes.
Is this a work in progress? Please explain why these constraints are put...