Displaying 7 results from an estimated 7 matches for "inputreg".
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inputregs
2007 Jan 06
6
PXE stack access via com32
...BX PXE function number
ES:DI PXE data buffer
Output: AX PXE return status code
or, in com32 terms (the PXE call argument struct has been copied into the bounce
buffer and the buffer field of the PXE call argument struct is setup to point into the bounce buffer as well):
inputRegs.es = SEG(__com32.cs_bounce);
inputRegs.edi.w[0] = OFFS(__com32.cs_bounce);
inputRegs.eax.w[0] = 0x0009;
/* call PXE stack */
inputRegs.ebx.w[0] = 0x0071;
/* PXENV_GET_CACHED_INFO opcode */
__intcall(0x22, &inputRegs, &outputRegs);
However, when setup this way, &...
2009 May 24
1
Sending UDP packets from comboot
...t_addr("255.255.255.255"); // inet_addr working here?
args.gw = inet_addr("0.0.0.0");
args.src_port = 4711;
args.dst_port = 4799;
args.buffer_size = <some sizeof() code>
args.buffer = <some stuff to put my data in>
memcpy(__com32.cs_bounce, &args, sizeof(args);
inputRegs.es = SEG(__com32.cs_bounce);
inputRegs.edi.w[0] = OFFS(__com32.cs_bounce);
inputRegs.eax.w[0] = 0x0009; /* call PXE stack */
inputRegs.ebx.w[0] = 0x0033; /* PXENV_UDP_WRITE opcode */
__intcall(0x22, &inputRegs, NULL);
// code end
Could anyone give me a hand on that?
Or is there any example...
2005 Jul 25
1
[LLVMdev] How to partition registers into different RegisterClass?
...: ConstFpReg<0, "c0">;
...
def C200 : ConstFpReg<199, "c200">;
def I0 : ConstIntReg<0, "i0">;
...
def I100 : ConstIntReg<100, "i100">;
def R0 : TempReg<0, "r0">;
def R32 : TempReg<31, "r32">;
def V0 : InputReg<0, "v0">;
..
def V10 : InputReg<9, "v10">;
def O0 : OutputReg<0, "o0">;
..
def O4 : OutputReg<4, "o4">;
def FloatingPointRC : RegisterClass<packed, 128,
[R0, R1, R2, ..., R32,
C0, C1, ..., C200,
V0, ..., V10,...
2009 May 28
1
Message 11 Syslinux Digest, Vol 74, Issue 24(Re: PXEboot trouble with Soekris 4826 (Miller, Shao)
...t_addr working here?
> args.gw = inet_addr("0.0.0.0");
> args.src_port = 4711;
> args.dst_port = 4799;
> args.buffer_size = <some sizeof() code>
> args.buffer = <some stuff to put my data in>
>
> memcpy(__com32.cs_bounce, &args, sizeof(args);
>
> inputRegs.es = SEG(__com32.cs_bounce);
> inputRegs.edi.w[0] = OFFS(__com32.cs_bounce);
> inputRegs.eax.w[0] = 0x0009; /* call PXE stack */
> inputRegs.ebx.w[0] = 0x0033; /* PXENV_UDP_WRITE opcode */
>
> __intcall(0x22, &inputRegs, NULL);
> // code end
>
> Could anyone give me a...
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2008 May 20
2
[LLVMdev] [ia64] Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")
...sn't handled and the function
returns
<pair>(0, NULL). However, it is explicitly called for that constraint by
llvm::SelectionDAGLowering::visitInlineAsm():
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs,
InputRegs);
Assuming the correct fix is to enhance
llvm::TargetLowering::getRegForInlineAsmConstraint(), can someone give
me
some pointers as to how to fix it? I have no experience with the code
and
like to get my hands dirty...
Thanks,
BTW: Is there a cross-reference of the project somewhere?
--
M...