Displaying 5 results from an estimated 5 matches for "input_ptr2".
Did you mean:
input_ptr0
2010 May 29
3
[LLVMdev] Vectorized LLVM IR
...ndvar
%fTemp0 = load float* %input_ptr1, align 4
%input_ptr0 = getelementptr float* %input0, i64 %indvar
%fTemp1 = load float* %input_ptr0, align 4
%fTemp2 = fadd float %fTemp1, %fTemp0
%input_ptr3 = getelementptr float* %input3, i64 %indvar
%fTemp3 = load float* %input_ptr3, align 4
%input_ptr2 = getelementptr float* %input2, i64 %indvar
%fTemp4 = load float* %input_ptr2, align 4
%fTemp5 = fadd float %fTemp4, %fTemp3
%fTemp6 = fmul float %fTemp5, %fTemp2
store float %fTemp6, float* %output_ptr0, align 4
%indvar.next = add i64 %indvar, 1
%exitcond = icmp eq i64 %indvar.next, %c...
2010 May 29
0
[LLVMdev] Vectorized LLVM IR
...nput0, i64 %indvar
> %fTemp1 = load float* %input_ptr0, align 4
> %fTemp2 = fadd float %fTemp1, %fTemp0
> %input_ptr3 = getelementptr float* %input3, i64 %indvar
> %fTemp3 = load float* %input_ptr3, align 4
> %input_ptr2 = getelementptr float* %input2, i64 %indvar
> %fTemp4 = load float* %input_ptr2, align 4
> %fTemp5 = fadd float %fTemp4, %fTemp3
> %fTemp6 = fmul float %fTemp5, %fTemp2
> store float %fTemp6, float* %output_ptr0, align 4
> ...
2010 May 29
1
[LLVMdev] Vectorized LLVM IR
...gt;> %fTemp1 = load float* %input_ptr0, align 4
>> %fTemp2 = fadd float %fTemp1, %fTemp0
>> %input_ptr3 = getelementptr float* %input3, i64 %indvar
>> %fTemp3 = load float* %input_ptr3, align 4
>> %input_ptr2 = getelementptr float* %input2, i64 %indvar
>> %fTemp4 = load float* %input_ptr2, align 4
>> %fTemp5 = fadd float %fTemp4, %fTemp3
>> %fTemp6 = fmul float %fTemp5, %fTemp2
>> store float %fTemp6, float* %output_ptr0...
2010 May 28
0
[LLVMdev] Vectorized LLVM IR
Hi Stéphane,
The SSE support is the LLVM backend is fine. What is the code that's generated? Do you have some short examples of where LLVM doesn't do as well as the equivalent scalar code?
-bw
On May 28, 2010, at 12:13 PM, Stéphane Letz wrote:
> Hi,
>
> We are experimenting directly generating vectorized LLVM IR (using <8 x float> kind of types), then compiling the code
2010 May 28
3
[LLVMdev] Vectorized LLVM IR
Hi,
We are experimenting directly generating vectorized LLVM IR (using <8 x float> kind of types), then compiling the code to SSE on a 64 bits machine. Right now the equivalent code in scalar mode sill outperform the SSE one.
What is the quality of the SSE support in X86 LLVL backend? Are they any specific things to be aware of to improve the speed?
Thanks
Stéphane Letz