Displaying 2 results from an estimated 2 matches for "initialcapability".
2015 Sep 07
2
POssible bug in the Arm code generator
...legal instruction.
> 0x03ff9dbc in stg_ap_v_fast ()
> (gdb) bt
> #0 0x03ff9dbc in stg_ap_v_fast ()
> #1 0x03fc6ce6 in StgRun (f=0x3ff9db4 <stg_ap_v_fast>, basereg=0x49d2090 <MainCapability+16>) at
> rts/StgCRun.c:81
> #2 0x03fca52a in schedule (initialCapability=0x49d2080 <MainCapability>, task=0x49e62c0) at
> rts/Schedule.c:524
> #3 0x03fcc5e6 in scheduleWaitThread (tso=0xb6c07000, ret=0x0, pcap=0xbeffeb74) at
> rts/Schedule.c:2429
> #4 0x03fbc7e4 in rts_evalLazyIO (cap=0xbeffeb74, p=0x402d470 <ZCMain_main_closur...
2015 Sep 06
2
POssible bug in the Arm code generator
Hi all,
I do a little work on the Glasgow Haskell Compiler (GHC) which uses
LLVM for the backend when compiling for Arm and some other targets.
The reason I am posting to this list is that a GHC compiled program
(using the LLVM backend) is getting an illegal instruction exception
on the this instruction:
ldr r0, [r0]
According to the Arm archtecture manual: