search for: inherits_vlen

Displaying 6 results from an estimated 6 matches for "inherits_vlen".

2018 Apr 16
1
RFC: Supporting the RISC-V vector extension in LLVM
...ector type and my proposal, e.g., by adding my proposed "vlentoken" to instructions on scalable vectors and encode the "unknown, but fixed at program load time" vectorlength (i.e., SVE) by using `token none` as vector length token. I think your proposed function attribute 'inherits_vlen' would allow for outlining for SVE without causing problems, possibly using a TTI function to determine whether that was reasonable based on the backend. I don't think a token is needed -- you can tell whether special care is needed when moving/copying an instruction between functions base...
2018 Apr 11
5
RFC: Supporting the RISC-V vector extension in LLVM
...cs Every time a function is called, a positive integer called the *dynamic vector length* is determined in an unspecified way. The dynamic vector length can differ not only between different functions, but also between different calls to the same function. The exception is that functions with the `inherits_vlen` attribute get the same dynamic vector length as their caller (Note: this attribute is a straw man, target-specific calling conventions may work better for this purpose). A new instruction `vlentoken` is added, which has no operands and is of type `token`. This token represents the dynamic vector...
2018 Apr 13
0
RFC: Supporting the RISC-V vector extension in LLVM
...sitive integer called the >> *dynamic vector length* is determined in an unspecified way. The dynamic >> vector length can differ not only between different functions, but also >> between different calls to the same function. The >> exception is that functions with the `inherits_vlen` attribute get >> the same dynamic vector length as their caller (Note: this attribute is a >> straw man, target-specific calling conventions may work better for this >> purpose). >> >> A new instruction `vlentoken` is added, which has no operands and is >> o...
2018 Apr 12
0
RFC: Supporting the RISC-V vector extension in LLVM
...ction is called, a positive integer called the *dynamic > vector length* is determined in an unspecified way. The dynamic vector > length can differ not only between different functions, but also between > different calls to the same function. The exception is that functions with > the `inherits_vlen` attribute get the same dynamic vector length as their > caller (Note: this attribute is a straw man, target-specific calling > conventions may work better for this purpose). > > A new instruction `vlentoken` is added, which has no operands and is of > type `token`. This token repres...
2018 Jul 02
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...so we can fully support these targets from the start. Without these generic intrinsics, we would either need to emit target specific ones or go through the painful process of VLA-style reduction trees with loops or the like. -- setting the vector length (MVL) -- I really like the idea of the `inherits_vlen` attribute. Absence of this attribute in a callee means we can safely stop tracking the vector length across the call boundary. However, i think there are some issues with the `vlen token` approach. * Why do you need an explicit vlen token if there is a 1 : 1-0 correspondence between functions...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi, Now that Sander has committed enough MC support for SVE, here's an updated RFC for variable length vector support with a set of 14 patches (listed at the end) to demonstrate code generation for SVE using the extensions proposed in the RFC. I have some ideas about how to support RISC-V's upcoming extension alongside SVE; I'll send an email with some additional comments on