search for: infocenter

...NT. I have tried scopy, xcopy and copying via GUI from the the NT directly to Samba but ACLs do not seem to flow properly. For example: On NT for a given file using the smbcacls command the perms are ACL:FESFOO\Domain Users:ALLOWED/0/READ ACL:BUILTIN\Administrators:ALLOWED/0/FULL ACL:FESFOO\InfoCenter:ALLOWED/0/FULL when the file or directory is copied to Samba the ACLs become ACL:FESFOO\root:ALLOWED/0/RW ACL:FESFOO\InfoCenter:ALLOWED/0/RW ACL:\Everyone:ALLOWED/0/ I can manually go in and fix these via a windows GUI but when I try to use smbcacls smbcacls -d 3 //spiderman-new/infocenter sti...

On 11/04/2013 11:15 AM, Eric Christopher wrote: > > > > On Mon, Nov 4, 2013 at 11:05 AM, Shankar Easwaran > <shankare at codeaurora.org <mailto:shankare at codeaurora.org>> wrote: > > Hi, > > I was looking at the ARM ABI > docs(http://infocenter.arm.__com/help/topic/com.arm.doc.__ihi0044e/IHI0044E_aaelf.pdf > <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf>) > and they mention. > > "A binary file may use REL or RELA relocations or a mixture of the > two (but multiple r...

...pu to fetch every instruction in a > function, queue them for execution under wait conditions, *then* fetch the > ISB? This would be a *really* weird implementation, but would it be legal > according to this spec? If so, the ISB provides *no* guarantees.) > > Reference: > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/CIHGHHIE.html You've actually linked to the assembler (as in "armasm") reference manual there. The architectural documentation of these barriers is better, though still not airtight in my opinion. From section A3.8.3, the bit about &...

...ric Christopher wrote: >> >> >> >> On Mon, Nov 4, 2013 at 11:05 AM, Shankar Easwaran >> <shankare at codeaurora.org <mailto:shankare at codeaurora.org>> wrote: >> >> Hi, >> >> I was looking at the ARM ABI >> docs(http://infocenter.arm.__com/help/topic/com.arm.doc.__ihi0044e/IHI0044E_aaelf.pdf >> <http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf>) >> and they mention. >> >> "A binary file may use REL or RELA relocations or a mixture of the >> two...

...ith 4.2 I get the following error: admin$ /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/clang -arch armv7 ./src/asm.s -o asm.o ./src/asm.s:30:5: error: instruction requires a CPU feature not currently enabled add r2, pc, r2 According to ARM <http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489c/Cihcjfjg.html> specification: [http://infocenter.arm.com/help/topic/com.arm.doc.common/images/triangle_down.png]Use of PC and SP in Thumb instructions In most of these instructions, you cannot use PC (R15) for Rd, or any operand. The exceptions...

Hi, I was looking at the ARM ABI docs(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf) and they mention. "A binary file may use REL or RELA relocations or a mixture of the two (but multiple relocations for the same address must use only one type)." Does LLVM emit rel/rela relocations with ARM ? Any tests ? Th...

...if they did occur. On Wed, Jan 13, 2016 at 10:59 AM, Tim Northover <t.p.northover at gmail.com> wrote: > > I haven't touched ARMv8 in a few years so I'm rusty on the non-temporal > > details for that ISA. I lifted this example from here: > > > > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html > > > > Which is correct? > > FWIW, I agree with John here. The example I'd give for the unexpected > behaviour allowed in the spec is: > > .Lwait_for_data: > ldr x0, [x3] > cbz x0, .Lwait_...

On Mon, Nov 4, 2013 at 11:05 AM, Shankar Easwaran <shankare at codeaurora.org>wrote: > Hi, > > I was looking at the ARM ABI docs(http://infocenter.arm. > com/help/topic/com.arm.doc.ihi0044e/IHI0044E_aaelf.pdf) and they mention. > > "A binary file may use REL or RELA relocations or a mixture of the two > (but multiple relocations for the same > address must use only one type)." > > Does LLVM emit rel/rela relocat...

...ted hello world against an old GCC distribution that has ARM only libraries that do not require interworking: arm-none-linux-gnueabi-gcc (CodeSourcery Sourcery G++ Lite 2007q1-10) 4.2.0. Documentation can be found in the ABI for the ARM Architecture, which is available on ARM's website: http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html The official instruction encodings are documented in the ARM Architecture Reference Manual. This is publically available from ARM but requires a free registration to download: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index....

Hi, I've got an assembly file which used to compile with previous clang versions. However with 4.2 I get the following error: admin$ /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin/clang -arch armv7 ./src/asm.s -o asm.o ./src/asm.s:30:5: error: instruction requires a CPU feature not currently enabled add r2, pc, r2 According to ARM

From reading the wiki for a filesystem quota, I took my shot at 1) building my binaries using the mods in AIXPluginsSupport 2) changing dovecot.conf and 3) putting the plugins in the library But I'm getting this error message when I invoke dovecot: Plugin imap_quota not found from directory /usr/local/lib/dovecot Error: imap dump-capability process returned 89 It would seem that a) I have

Hi, I'm building a new backend which can only load very limited range of imm. So I decided to use constant pool, and place constant pool entries close enough to instructions use the entries (we have very limited range PC-relative memory load). However, lld & llc output the object files that gather all constant pool entries into one section. How can I make them mix these entries into code

....] b past_literals special_lit_sym: .word variable_desired past_literals: [...instructions...] In general, deciding whether to disassemble a given location as code or data is a very hard problem (think of all the evil tricks you could play with dual-purpose), so the ARM ELF ABI (http://infocenter.arm.com/help/topic/com.arm.../IHI0044D_aaelf.pdf) specifies something called mapping symbols, which assemblers should insert to tell disassemblers what's actually needed. The idea is that a $a should be inserted at the start of each section of ARM code, $t before Thumb and $d before data (incl...

Hi - One item that came up at the European User Group Meeting on Sept 16th was how to get information about the ARM Instruction Set. ARM has a Manual (in several volumes) called the ARM Architectural Reference Manual which covers the instruction and you can download from here: infocenter.arm.com In order to download it you do need to register with the infocenter website (Name, Company, Email address, country where you live) and you do need to click-thru an agreement which states you don't intend to use the document for the purpose of investigating if the ISA violates patents....

...as --apcs=... options that can tell it it's compiling PIC code). I can't recall a similar command-line option to llvm-mc, but Clang-as-assembler probably accepts -fPIC. Goodness knows whether we want to do anything with it though. (from Jim) > What does ARM’s documentation say? http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473c/Bgbbfgia.html Fairly similar, though it doesn't seem to use a MOV opportunistically. Tim.

I'm attempting to detect encoding bugs by comparing disassembly when using GCC's 'as' versus LLVM's integrated assembler. Generally this has gone very well, but one thing that adds a lot of noise is that .word marked as a R_ARM_ABS32 is disassembled as an instruction and not data. Please see the attached 'dump.diff' which was generated by diffing the "objdump -d

...k\n" ^ <inline asm>:1:14: note: instantiated into assembly here mrs r5, primask ^ This appears to be due to llvm lacking support for the various cortex-m{3,4} special registers. ("primask", "faultmask", etc) http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/ch05s13s01.html Can someone tell me how I would go about adding support for these special registers? -Kurt

...at the moment. :) > I wonder if ARM32 BE is a real thing. I know that the processor is > bi-endian, but is there any system that uses ARM32 in big-endian mode? Yes... it is "a thing". :) ARM has two modes: BE32 and BE8 (mixed) and they can be enabled via CP15 registers. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/ch06s05s01.html cheers, --renato

I had a post since 1 week and i want to know why i cant play to Dragon Age2 I'am with Playonlinux 1.3.15, the game i purchast it to Wallmart. When i see the game on Playonlinux i go for search it, i installed it i cant play because Playonlinux tell me to bypass the anti-hacking. I said WHAT'S THAT?. It's the first time i see it for a l?gal game, can you help me please or explain this

I think __aeabi is ARM EABI not Android EABI, e.g. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0043d/index.html. The problem is not that the __aeabi functions are missing on Android, they're defined in libgcc.a, the problem is that they don't get linked in unless they're referenced. I don't know how this problem is avoided on A...