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[LLVMdev] [Polly] Aliasing problems escalation (WAS: Re: [DragonEgg] [Polly] Should we expect DragonEgg to produce identical LLVM IR for identical GIMPLE?)
2013 Jan 04
4
[LLVMdev] [Polly] Aliasing problems escalation (WAS: Re: [DragonEgg] [Polly] Should we expect DragonEgg to produce identical LLVM IR for identical GIMPLE?)
...op.9.ll --- array.loop.9.ll 2013-01-04 01:37:40.312259953 +0100 +++ module_array.loop.9.ll 2013-01-04 01:37:50.036259544 +0100 @@ -12,34 +12,39 @@ br label %"10.cloned" "16.cloned": ; preds = %"15.cloned" - %1 = add i64 %indvar3, 1 - %exitcond12 = icmp eq i64 %1, 64 - br i1 %exitcond12, label %"17.exitStub", label %"10.cloned" + %1 = add i64 %indvar1, 1 + %exitcond9 = icmp eq i64 %1, 64 + br i1 %exitcond9, label %"17.exitStub", label %"10.cloned" "10.cloned":...