Displaying 3 results from an estimated 3 matches for "indexmodenon".
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indexmodenone
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
...like:
// A list of registers separated by comma. Used by load/store multiple.
def reglist : Operand<i32> {
let PrintMethod = "printRegisterList";
}
def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeNone, LdStMulFrm, IIC_iLoadm,
"ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
Tablegen produces an instruction description with 5 input operands: 2 for $addr, 2 for $p, and 1 for $dsts. But $dsts and the following variable_ops are all outputs!
The description...
2010 Mar 19
0
[LLVMdev] Instruction with variable number of outputs
...parated by comma. Used by load/store multiple.
> def reglist : Operand<i32> {
> let PrintMethod = "printRegisterList";
> }
>
> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
> reglist:$dsts, variable_ops),
> IndexModeNone, LdStMulFrm, IIC_iLoadm,
> "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
>
> Tablegen produces an instruction description
Ok, you mean TargetInstrDesc, right?
> with 5 input operands: 2 for $addr, 2 for $p, and 1 for $dsts. But $dsts and the...
2010 Mar 19
2
[LLVMdev] Instruction with variable number of outputs
...load/store multiple.
>> def reglist : Operand<i32> {
>> let PrintMethod = "printRegisterList";
>> }
>>
>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p,
>> reglist:$dsts, variable_ops),
>> IndexModeNone, LdStMulFrm, IIC_iLoadm,
>> "ldm${addr:submode}${p}\t$addr, $dsts", "", []>;
>>
>> Tablegen produces an instruction description
>
> Ok, you mean TargetInstrDesc, right?
Yes.
>> with 5 input operands: 2 for $addr, 2 for $p, and...