Displaying 4 results from an estimated 4 matches for "incrementsize".
2010 May 05
2
[LLVMdev] SplitVecRes_LOAD
I was going through the function DAGTypeLegalizer::SplitVecRes_LOAD in
LegalizeVectorTypes.cpp. I noticed that it is using getSizeInBits()/8
to compute IncrementSize, which is the offset for the load of second
half of the vector. I have a situation where the frontend is producing
load for a <2 x i1> type, and the architecture has i1 registers (but
not v2i1 registers). The store size of i1 is 8 bits (the size returned
by getStoreSizeInBits()). When SplitVe...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...tTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
- SVOffset, ST->getMemoryVT(),
- isVolatile, Alignment);
- break;
- }
- // Fall thru to expand for vector
- case Expand: {
- unsigned IncrementSize = 0;
- SDValue Lo, Hi;
-
- // If this is a vector type, then we have to calculate the increment as
- // the product of the element size in bytes, and the number of elements
- // in the high half of the vector.
- if (ST->getValue().getValueType().isVector()) {
-...