search for: incdec

....i.i, label %for.cond.preheader.i.i, label %if.end.i for.cond.preheader.i.i: ; preds = %if.end %cmp5.i.i = icmp eq i16 %4, 0 br i1 %cmp5.i.i, label %for.inc.i.i, label %eisneg.exit for.inc.i.i: ; preds = %for.cond.preheader.i.i %incdec.ptr.i.i = getelementptr inbounds [13 x i16]* %e, i32 0, i32 1 %5 = load i16* %incdec.ptr.i.i, align 2, !tbaa !5 %cmp5.1.i.i = icmp eq i16 %5, 0 br i1 %cmp5.1.i.i, label %for.inc.1.i.i, label %eisneg.exit for.inc.1.i.i: ; preds = %for.inc.i.i %incdec.ptr.1...

...target instruction - as can be seen at the bottom. I would appreciate any input on this, and if needed I can supply a test case. /Jonas Loop before vectorize pass: while.body320: ; preds = %while.body320.preheader, %while.body320 %dl.0291 = phi i64* [ %incdec.ptr335, %while.body320 ], [ %73, %while.body320.preheader ] %ll.0290 = phi i64* [ %incdec.ptr332, %while.body320 ], [ %74, %while.body320.preheader ] %rl.0289 = phi i64* [ %incdec.ptr333, %while.body320 ], [ %75, %while.body320.preheader ] %len.0288 = phi i32 [ %dec, %while.body320 ], [...

Hello, I found that GVN doesn't promote identical sequence of instructions in if and else branch to their common predecessors. For example, for the following code snippet pred: … br i1 %cmp, label %if, label %else if: %incdec.ptr.1 = getelementptr inbounds i8, i8* %ptr, i64 1 %cast1 = ptrtoint i8* %incdec.ptr.1 to i64 … else: %incdec.ptr.2 = getelementptr inbounds i8, i8* %ptr, i64 1 %cast2 = ptrtoint i8* %incdec.ptr.2 to i64 GVN doesn't move instructions in 'if' and 'else' blocks to '...

...und 82 pair connections. BBV: selected pairs in the best tree for: %0 = load i8* %r.063, align 1, !tbaa !0 BBV: selected pair: %mul23 = mul nsw i32 %conv14, 234 <-> %mul35 = mul nsw i32 %conv15, 543 BBV: selected pair: %0 = load i8* %r.063, align 1, !tbaa !0 <-> %1 = load i8* %incdec.ptr11, align 1, !tbaa !0 BBV: selected pair: %conv14 = zext i8 %0 to i32 <-> %conv15 = zext i8 %1 to i32 BBV: selected pair: %add26 = add i32 %mul25, %mul23 <-> %add36 = add i32 %mul35, %mul33 BBV: selected pair: %mul = mul nsw i32 %conv14, 123 <-> %mul16 = mul nsw i32...

On Thu, 2012-01-26 at 15:12 -0600, Sebastian Pop wrote: > On Thu, Jan 26, 2012 at 2:49 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > Thanks! Did you compile with any non-default flags other than -mllvm > > -vectorize? > > I used -O3 and -vectorize, no other non-default flags. If I run clang -O3 -mllvm -vectorize -S -emit-llvm -o test.ll test.c then I get no

...lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: Hello, I found that GVN doesn't promote identical sequence of instructions in if and else branch to their common predecessors. For example, for the following code snippet pred: … br i1 %cmp, label %if, label %else if: %incdec.ptr.1 = getelementptr inbounds i8, i8* %ptr, i64 1 %cast1 = ptrtoint i8* %incdec.ptr.1 to i64 … else: %incdec.ptr.2 = getelementptr inbounds i8, i8* %ptr, i64 1 %cast2 = ptrtoint i8* %incdec.ptr.2 to i64 GVN doesn't move instructions in 'if' and 'else' blocks to '...

On Thu, Jan 26, 2012 at 3:41 PM, Hal Finkel <hfinkel at anl.gov> wrote: > On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote: >> arm-none-linux-gnueabi > > Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get Minor remark: please use -target instead of -ccc-host-triple that is now deprecated. Thanks for looking at this testcase. Sebastian -- Qualcomm

...into more complicated bits. An example of the debug output I get for my earlier example: LV: Checking a loop in "fn1" LV: Found a loop: for.body == Induction == LV: Found an induction variable. == Our write reduction == LV: Found a pointer add reduction PHI. %WRITE913 = phi i8* [ %incdec.ptr18, %for.body ], [ %WRITE, %for.body.preheader ] == Not sure what this is... Will check. == LV: Found an non-int non-pointer PHI. == Our read reduction == LV: Found a pointer add reduction PHI. %READ1012 = phi i8* [ %incdec.ptr2, %for.body ], [ %READ, %for.body.preheader ] == Below are the...

On Thu, 2012-01-26 at 15:36 -0600, Sebastian Pop wrote: > arm-none-linux-gnueabi Indeed, adding -ccc-host-triple arm-none-linux-gnueabi I also get vectorization (even though I don't get vectorization when targeting x86_64). I'll let you know what I find. -Hal -- Hal Finkel Postdoctoral Appointee Leadership Computing Facility Argonne National Laboratory

...t; if and else branch to their common predecessors. For example, for the >>> following code snippet >>> >>> >>> pred: >>> >>> … >>> >>> br i1 %cmp, label %if, label %else >>> >>> if: >>> >>> %incdec.ptr.1 = getelementptr inbounds i8, i8* %ptr, i64 1 >>> >>> %cast1 = ptrtoint i8* %incdec.ptr.1 to i64 >>> >>> … >>> >>> else: >>> >>> %incdec.ptr.2 = getelementptr inbounds i8, i8* %ptr, i64 1 >>> >>> %cas...

...utput I get for my earlier example: > > LV: Checking a loop in "fn1" > LV: Found a loop: for.body > > == Induction == > > LV: Found an induction variable. > > == Our write reduction == > > LV: Found a pointer add reduction PHI. %WRITE913 = phi i8* [ %incdec.ptr18, %for.body ], [ %WRITE, %for.body.preheader ] > > == Not sure what this is... Will check. == > > LV: Found an non-int non-pointer PHI. > > == Our read reduction == > > LV: Found a pointer add reduction PHI. %READ1012 = phi i8* [ %incdec.ptr2, %for.body ], [ %READ,...

...IR for the loop and the SCEV dump: for.body: ; preds = %for.body.lr.ph, %for.body %i.07 = phi i32 [ 0, %for.body.lr.ph ], [ %add1, %for.body ] %s.06 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ] %a.addr.05 = phi i32* [ %a, %for.body.lr.ph ], [ %incdec.ptr, %for.body ] %incdec.ptr = getelementptr inbounds i32* %a.addr.05, i64 1 %0 = load i32* %a.addr.05, align 4, !tbaa !0 %add = add i32 %0, %s.06 %add1 = add nsw i32 %i.07, 4 %cmp = icmp slt i32 %add1, %len br i1 %cmp, label %for.body, label %for.cond.for.end_crit_edge Classifying ex...

...if (!*c) break; ++c; } while (*c); } And in IR form: define void @test(i8* nocapture %c) { entry: %.pre = load i8* %c, align 1 br label %do.body do.body: %0 = phi i8 [ %.pre, %entry ], [ %1, %if.end ] %c.addr.0 = phi i8* [ %c, %entry ], [ %incdec.ptr, %if.end ] %tobool = icmp eq i8 %0, 0 br i1 %tobool, label %do.end, label %if.end if.end: %incdec.ptr = getelementptr inbounds i8* %c.addr.0, i64 1 %1 = load i8* %incdec.ptr, align 1 %tobool1 = icmp eq i8 %1, 0 br i1 %tobool1, label %do.end, label %do.bod...

...utput I get for my earlier example: > > LV: Checking a loop in "fn1" > LV: Found a loop: for.body > > == Induction == > > LV: Found an induction variable. > > == Our write reduction == > > LV: Found a pointer add reduction PHI. %WRITE913 = phi i8* [ %incdec.ptr18, %for.body ], [ %WRITE, %for.body.preheader ] > > == Not sure what this is... Will check. == > > LV: Found an non-int non-pointer PHI. > > == Our read reduction == > > LV: Found a pointer add reduction PHI. %READ1012 = phi i8* [ %incdec.ptr2, %for.body ], [ %READ,...

On Sep 10, 2013, at 8:59 AM, Robert Lytton <robert at xmos.com> wrote: > Hi, > > A bit more information. > I believe my problem lies with the fact that the load is left as 'anyext from i8'. > On the XCore target we know this will become an 8bit zext load - as there is no 8bit sign extended load! > If BB#1 were to force the load to a "zext from i8" would

Dear list members, Could anyone tell me if there is an equivalent of the Matlab declaration 'persistant' in R? Thank you very much, Bernard Gregorry. (Matlaber converted to R). --------------------------------- [[alternative HTML version deleted]]

> How are you compiling this? I get the following sort of output: > > llvm-gcc incdec.cpp -o incdec I am currently using LLVM 1.8 -- I was basically holding off porting until LLVM 2.0 stabilises because I want to be able to move to 64 bit Intel and don't want to have to hit a moving target. > void %inc(int* %p) { > entry: > %tmp = volatile load int* %p...

...dump: > > for.body: ; preds = > %for.body.lr.ph, %for.body > %i.07 = phi i32 [ 0, %for.body.lr.ph ], [ %add1, %for.body ] > %s.06 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ] > %a.addr.05 = phi i32* [ %a, %for.body.lr.ph ], [ %incdec.ptr, %for.body > ] > %incdec.ptr = getelementptr inbounds i32* %a.addr.05, i64 1 > %0 = load i32* %a.addr.05, align 4, !tbaa !0 > %add = add i32 %0, %s.06 > %add1 = add nsw i32 %i.07, 4 > %cmp = icmp slt i32 %add1, %len > br i1 %cmp, label %for.body, label %for.cond...

...%no_final.1 = phi i32 [ %no_final.055, %while.body ], [ 1, %if.end29 ], [ %no_final.055, %sw.bb20 ], [ %no_final.055, %sw.bb15 ], [ %no_final.055, %sw.bb10 ], [ %no_final.055, %sw.bb6 ], [ %no_final.055, %sw.bb2 ], [ %no_final.055, %sw.bb ] %locinput.1 = phi i8* [ %locinput.057, %while.body ], [ %incdec.ptr, %if.end29 ], [ %locinput.057, %sw.bb20 ], [ %locinput.057, %sw.bb15 ], [ %locinput.057, %sw.bb10 ], [ %locinput.057, %sw.bb6 ], [ %locinput.057, %sw.bb2 ], [ %locinput.057, %sw.bb ] %next30 = getelementptr inbounds %struct.Node, %struct.Node* %scan.056, i64 0, i32 0, !dbg !91 %8 = load %st...

...; preds = %for.body ret void } define void @Init2(i32* %p, i32* %e) nounwind { entry: %cmp1 = icmp eq i32* %p, %e br i1 %cmp1, label %while.end, label %while.body while.body: ; preds = %entry, %while.body %p.addr.02 = phi i32* [ %incdec.ptr, %while.body ], [ %p, %entry ] %incdec.ptr = getelementptr inbounds i32* %p.addr.02, i32 1 store i32 4, i32* %p.addr.02, align 4, !tbaa !0 %cmp = icmp eq i32* %incdec.ptr, %e br i1 %cmp, label %while.end, label %while.body while.end: ; preds = %wh...